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Universal Verification Methodology (UVM)-System Verilog Workshop

23 Aug 2013 - 23 Aug 2013 9:30 AM  
Cadence益華電腦 新竹辦公室  
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he Universal Verification Methodology (UVM) is the first truly open, interoperable, and proven verification methodology. The UVM is an open-source SystemVerilog class library and methodology that defines a framework for reusable verification IP (VIP) and tests. It is 100% IEEE 1800 SystemVerilog and provides building blocks (objects) and a common set of verification-related utilities. The UVM release will be under the Apache 2.0 license, enabling anyone to use UVM libraries for any purpose, including creation of derivative work.
-09:00-10:00: Coverage Driven Verification
-10:00-11:00: Stimulus Generation
–11:00-12:00: Building Reusable Verification Components
–13:p00-14:00: Testbench Creation Using Reusable Components
–14:00-15:00: Coverage analysis and regression
–15:00: Summary

Questions About this Event?Send email to training_taiwan@cadence.com

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