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Universal Verification Methodology (UVM)-System Verilog Workshop

 
活動類型:
Workshop  
活動日期:
14 Nov 2014 - 14 Nov 2014 9:30 AM  
活動地點:
新竹益華電腦辦公室 (科學園區篤行路6-5號2F)  
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Expectations

        Start building knowledge on the Universal Verification Methodology (UVM)

       We will cover many of the basic UVM concepts

       You will test some UVM features with simple labs

       See how UVM is supported by Cadence verification platform

       Understand how Coverage Driven Methodology (CDV) works with UVM

        The workshop will not cover

       SystemVerilog language syntax

 

Agenda

Course Time: 09:30 AM – 04:30 PM

• Introduction to UVM and Coverage Driven Verification

• UVM Class-based Workshop:

        The UVM Library

        Stimulus Generation

        Building Reusable Verification Components

        Testbench Creation Using Reusable Components

        Coverage Analysis and Regression

• UVM Multi-Language and UVM Acceleration

• Migration to UVM

• Summary

• Labs


Questions About this Event?Send email to training_taiwan@cadence.com

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