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最新活動


 
CPF 1.0 Workshop (1:30-5:30)
01 Jun 2012
想了解Common Power Format (CPF) 1.1 的功能嗎? 想知道CPF 1.1如何成就眾多設計成功案例嗎? 我們將展現CPF 1.1的設計流程，趕快參加Cadence益華電腦免費的CPF1.1的產品技術體驗營吧。
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Universal Verification Methodology (UVM)-System Verilog Workshop
15 Jun 2012
The Universal Verification Methodology (UVM) is the first truly open, interoperable, and proven verification methodology. The UVM is an open-source SystemVerilog class library and methodology that defines a framework for reusable verification IP (VIP) and tests. It is 100% IEEE 1800 SystemVerilog and provides building blocks (objects) and a common set of verification-related utilities. The UVM release will be under the Apache 2.0 license, enabling anyone to use UVM libraries for any purpose, including creation of derivative work.
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新竹分公司(Sales Office)
新竹市科學工業園區篤行路6-5號2F (2F,No. 6-5, Du Sing Rd., Hsinchu Science Park,Hsinchu City,Taiwan)
TEL ： 03-577-8951
FAX ： 03-578-0422
免付費專線： 0800-351-589
website : www.cadence.com.tw
Taiwan Event

Taiwan Event