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India University Program Policies | University Program Product Bundles | Training Offerings | Member Universities | India Foundry Services
Greetings from the Cadence India Team!
Chip design in India has moved into the big league with multinationals, design services companies, product companies and start-ups in the country growing by the day. Senior semiconductor executives, as well as trade bodies such as NASSCOM, see this as a sunrise industry, with the only impediment being a potential shortfall of quality VLSI-trained talent.
Therefore, for many years, Industry, Government and Academia have worked together to build the manpower pool, with the aim of making India a VLSI Design powerhouse in the global semiconductor world.
As the leader in the electronic design automation (EDA) industry, Cadence has been at the heart of this effort, providing its tools to engineering institutes at rates they can afford.
Why?
Because Cadence is committed to helping its customers by providing them with a pool of engineers experienced in EDA tool use and methodologies.
IntroductionTalent is of essence in a knowledge-intensive sector like electronic design. India produces a large number of electronics and computer science graduate engineers every year. However, while there is no dearth of manpower, the challenge is finding “design aware” engineers who are trained specifically in VLSI design and can ramp up quickly. Simply put, the industry is facing a “quality gap” with regard to talent.
Getting fresh graduates ramped up quickly to productivity is a key concern across the industry ecosystem. Several companies have already taken these and other steps to give students real-life experience before they graduate, thereby lessening ramp up time when they enter the industry.
When Cadence established its Indian presence over 20 ago, we realized early on the need to nurture and develop the country’s talent pool through public-private partnerships at various levels. Some of them are mentioned here.
Cadence University ProgramCadence also launched a university program which now has more than 300 institutes enrolled across India, including IITs, NITs and private engineering colleges. This program aims at giving institutes commercial-grade software so that students get access to best-in-class technology.
It is important to not only focus on the students, but the faculty as well. Cadence’s “Faculty Development Program” ensures that faculty is conversant with the latest Cadence technologies so that they are equipped to teach better.
Cadence Design ContestLaunched in 2006, the Cadence Design Contest has gained tremendous traction within the student community. The Contest aims at fostering innovation in design and is open to undergraduate and graduate students. Students can submit abstracts on operational chip design as well as conceptual design, and are judged by an Expert Committee consisting of Cadence and industry experts.
In 2010, due to the tremendous response from the student community, the Design Contest was divided into two categories – Master’s and Bachelor’s. A winner and runner up were selected from both categories.
Previous winners and runners-up:
| 2006 |
Sri Sant Gajanan Maharaj Institute of Technology, Shegaon |
Design and Implementation of Low Cost Power Optimised OTA Based FPAA in 0.35um Mixed-Mode CMOS Process |
Winner |
| 2007 |
IIT Kharagpur |
Design & Implementation Of An On-Chip Single Inductor Triple Output DC-DC Buck Converter |
Winner |
| 2007 |
I2IT Pune |
Reconfigurable Floating Point Unit |
Runner Up |
| 2008 |
IIIT Hyderabad |
Design of a Low Power Variable-Resolution Flash Type- ADC |
Winner |
| 2008 |
VESIT Mumbai |
Low Power AES Crypto Engine With Resistance to DPA Attacks |
Runner Up |
| 2009 |
IIT Delhi |
Design of Low-Power and High-Performance Ternary Content Addressable Memory (TCAM) |
Winner |
| 2009 |
BVB College of Engineering, Hubli |
Control Scheme for 1.8V, 2MHz Buck Converter Using Type II PI Controller |
Runner Up |
| 2010 |
IIT Kharagpur |
Low Power and High Speed Realization of Modified Fast Radon Transform using FFT – IFFT ASIC |
Winner - Master's Category |
| 2010 |
VESIT Mumbai |
Implementation of High Speed Vedic Co-Processor Incorporated With a 32 Bit Processor Executing RISC Instruction Set Architecture |
Winner - Bachelor's Category |
| 2010 |
IIT Bombay |
General Purpose Ultra Energy Efficient Programmable Analog Signal Conditioning IC” |
Runner Up - Master's Category |
| 2010 |
Jadavpur University |
ASIC Chip Development of Inverse Delayed Function Model of Neuron |
Runner Up - Bachelor's Category |
Cadence VLSI Certification Program (CVCP)The CVCP is a unique, one-of-a-kind program that bridges the gap between inexperienced engineering students and the industry need for “design aware”, trained manpower.
The program offers:
- World class curriculum that enables graduates to be industry-ready
- Access to best-in-class Cadence technologies and ecosystem partners
- An incremental training approach starting with VLSI basics and building up to industry-relevant skills
- Access to industry experts who deliver the curriculum
- More than 200 hours of theory PLUS labs study – to ensure that students get hands-on experience while reinforcing the basics
- Tool training and soft skills training
- Conducted in the campus during weekends, to be most convenient for the students
- Participants are eligible to apply for the prestigious Cadence Internship Program
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