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 Product Bundles 

 
India University Program | Training Offerings | India University Program Policies | Member Universities | India Foundry Services

We currently offer the following software configurations:

  Description Users
Bundle 1 University Bundle Analog Suite FE & BE 20
Bundle 2 University Bundle Digital Suite FE & BE 20
Bundle 3 University Bundle Analog & Digital FE &BE (for UG courses) 20
Bundle 4 University Bundle Digital FE 20
Bundle 5 University Bundle Full Suite 20

Suggested System Requirements and Lab Set-up

Operating System Hardware Requirements Software Requirements
Hard Disk Space Size of the RAM
Minimum (GB) Recommended (GB) Minimum (GB) Recommended (GB)
LINUX Server: 30

Clients:
30
Server: 50

Clients:
50
Server: 2

Clients:
2
Server: 4

Clients:
2
Operating System – RHEL- 5 (Update 1, 2, or 3)

Along with these, below mentioned are some other requirements that are required for the set-up.
  • Firewall should be disabled on all the client machines and the server.
  • Server as well as the client machines should be assigned a static IP address and a hostname.
  • All the client machines should be able to ping the server with the IP address of the server as well as the hostname of the server with 0% packet loss. (Please use ping command.)
  • The client machines should also ping themselves with their respective hostname and the IP address.
  • Client machines’ date and time should be in proper sync with the server’s.
  • A separate login can be created for the root and the user in the client machines.
  • Ftp and telnet should be enabled.
  • Server should have a DVD reader.
Configuration

Bundle 1: University Bundle Analog Suite FE & BE
90003 Virtuoso® Multi-mode Simulation with AP Simulator
95115 Virtuoso Schematic Editor XL
95210 Virtuoso Analog Design Environment XL
95310 Virtuoso Layout Suite XL
96210 Cadence Physical Verification System Design Rule Checker XL
96220 Cadence Physical Verification System Layout vs. Schematic Checker XL
QRCX300 Virtuoso QRC Extraction - XL
Advanced Options
95321 Virtuoso Layout Suite - GXL
95220 Virtuoso Analog Design Environment - GXL
21060 Virtuoso Schematic VHDL Interface
21400 Virtuoso Schematic Editor Verilog Interface
34580 Virtuoso Analog ElectronStorm Option
34570 Virtuoso Analog VoltageStorm Option
96240 Cadence Physical Verification System Results Manager
96250 Cadence Physical Verification System Graphic LVS Debugger
96260 Cadence Physical Verification System Interactive Short Locator Option
QRCX320 Cadence QRC Advanced Modeling GXL Option
VST1 VoltageStorm (transistor)
LPA108 Litho Physical Analyzer
LEA108 Litho Electrical Analyzer

Bundle 2: University Bundle Digital Suite FE & BE
29651 Incisive® Enterprise Simulator - XL
RC200 Encounter® RTL Compiler - XL
ET020 Option to RC - DFT Architect Basic
ET021 Option to RC - DFT Architect Advanced
ET022 Encounter True Time ATPG Basic
ET023 Encounter True Time ATPG Advanced
CFM500 Encounter Conformal Low Power - XL
Advanced Options
RC300 Encounter RTL Compiler - GXL option
RC400 Encounter RTL Compiler with physical
Back End
EDS200 Encounter Digital Implementation System XL
EDS10 Encounter Low Power GXL Option
EDS20 Encounter Mixed Signal GXL Option
EDS30 Encounter Advanced Node GXL Option
ELC200 Encounter Library Characterizer - XL
EPS200 Encounter Power System XL
FE725 Encounter Timing System-XL
VSDG Dynamic Gate Option to VoltageStorm PE
96210 Cadence Physical Verification System Design Rule Checker XL
96220 Cadence Physical Verification System Layout vs. Schematic Checker XL
QRCX300 Virtuoso QRC Extraction - XL

Bundle 3: University Bundle Analog & Digital FE &BE (for UG courses)
90003 Virtuoso Multi-mode Simulation with AP Simulator
95115 Virtuoso Schematic Editor XL
95210 Virtuoso Analog Design Environment XL
95310 Virtuoso Layout Suite XL
29651 Incisive Enterprise Simulator - XL
3002 Virtuoso Digital Implementation
96210 Cadence Physical Verification System Design Rule Checker XL
96220 Cadence Physical Verification System Layout vs. Schematic Checker XL
QRCX100 Virtuoso QRC Extraction - L

Bundle 4: University Bundle Digital FE
29651 Incisive Enterprise Simulator - XL
RC200 Encounter RTL Compiler - XL
ET020 Option to RC - DFT Architect Basic
ET021 Option to RC - DFT Architect Advanced
ET022 Encounter True Time ATPG Basic
ET023 Encounter True Time ATPG Advanced
CFM500 Encounter Conformal Low Power – XL
Advanced Options
RC300 Encounter RTL Compiler - GXL option
RC400 Encounter RTL Compiler with physical

Bundle 5: Full Suite
The Custom Integrated Circuit Bundle
Design Environment
Virtuoso AMS Designer Environment 70000
Virtuoso Analog Design Environment - XL 95210
Design Entry
Virtuoso Simulation Environment 206
Cadence SKILL Development Environment 900
Virtuoso Schematic VHDL Interface 21060
Virtuoso Schematic Editor Verilog Interface 21400
Virtuoso Schematic Editor - XL 95115
Virtuoso Analog Oasis Run-Time Option 32100
Cadence Design Framework Integrator's Toolkit 12141
Layout
Virtuoso Layout Suite - GXL1 95321
Cadence Chip Assembly Router2 3300
Physical Verification
Assura® Design Rule Checker 72110
Assura Layout vs. Schematic Verifier 72120
Virtuoso QRC Extraction - XL QRCX300
Virtuoso Advanced Analysis GXL option QRCX310
Cadence Assura Graphical User Interface Option 72140
Cadence Assura Multiprocessor Option 72150
Pcell Generator PASPCG
Graphical Technology Editor PASGTE
Cadence Physical Verification System Design Rule Checker XL 96210
Cadence Physical Verification System Layout vs. Schematic Checker XL 96220
Cadence Design Framework II 111
Circuit Simulation
Virtuoso Analog Design Environment - GXL 95220
Virtuoso Spectre® Circuit Simulator 38500
Virtuoso UltraSim Full-chip Simulator MMSIM72 33500
Virtuoso Spectre RF Simulation Option for 38520
Virtuoso RelXpert 33580
AMS Designer with Flexible Analog Simulation 70020
Virtuoso Multi-mode Simulation with AP Simulator 90003
Interfaces
Cadence Design Framework Integrator’s Toolkit 12141
Digital Integrated Circuits Bundle
Formal Verification
Encounter Conformal - CONFRML91 GXL CFM300
Synthesis
Encounter RTL Compiler - XL RC 101 RC200
Encounter RTL Compiler - GXL option RC 101 RC300
Encounter RTL Compiler with physical RC 101 RC400
Test
Architect Advanced Option to RC ET91 ET021
Encounter True Time Test Advanced ET91 ET023
Encounter Diagnostics Engine - XL ET91 ET009
Chip Planning
Cadence InCyte Chip Estimator XL CICE40 CPS200
Verification Bundle
Functional Verification
Cadence Simulation Analysis Environment (SimVision) IUS82 25010
Incisive Enterprise Simulator 29651 IES82 29651
Enterprise Simulator - XL Interface for MTI IES82 29661
Enterprise Simulator - XL Interface for VCS IES82 29671
Incisive Formal Verifier IFV82 23560
Incisive Enterprise Verifier – XL IFV82 IEV101
Incisive Software Extensions INCISV102 ISX100
Virtuoso AMS Designer Verification Option INCISV102 70030
Verification Process Automation
Incisive Enterprise Manager EMGR82 EMG100
Incisive VIP Portfolio VI VIP100
Litho Physical Analyzer LPA108
Litho Electrical Analyzer LEA108
Design for Manufacturing
VoltageStorm (transistor) ANLS62 VST1
Encounter Power System - L ETS91 EPS100
Signal Integrity
Encounter Timing System - XL ETS91 FE725
PacifIC Static Noise Analyzer for Custom Digital ICs PACIFIC61 CM00100
Encounter Timing System - L ETS91 FE625
Encounter Library Characterizer- XL ETS91 ELC200
Silicon Virtual Prototyping
Encounter Digital Implementation System - XL EDI91 EDS200
Encounter Low Power GXL Option EDI91 EDS10
Encounter Advanced Node GXL option EDI91 EDS30
Digital System-In-Product (SIP)1
Cadence SiP Digital Architect - GXL SPB163 SIP125
Cadence SiP Digital SI - XL SIP215 SPB163 SIP215
Cadence Chip Integration Option SIP625 SPB163 SIP625
Silicon-Package-Board Products
PCB Design and Layout
Allegro® PCB Librarian - XL PX3500 SPB163 PX3500
Allegro PCB Design HDL - XL PX3700 SPB163 PX3700
Allegro PCB Design CIS - XL PX3710 SPB163 PX3710
PCB High-Speed Analysis
Allegro PCB SI - XL PX3100 SPB163 PX3100
IC Packaging
Cadence SiP Layout – XL SIP225 SPB163 SIP225
Simulation
Allegro AMS Simulator1 PS2200 SPB163 PS2200