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Home > Solutions > System-to-Silicon Verification Solution

 System-to-Silicon Verification Solution  

  • Overview
  • Early Software Development
  • IP Design and Verification
  • SoC/Subsystem Integration & Verification
  • Hardware/Software Validation
  • Gate-Level Validation
  • System and Silicon Validation
App-Driven Market Increasing End-Product Complexity As electronic products across all market segments become more sophisticated, developing their underlying hardware and software, and integrating the two sides, continues to grow more complex. Early software development, hardware verification, hardware/software integration, and integrated system validation have become primary challenges, increasing development costs, project schedules, and risks.

The Challenge: On-Time Delivery of a Verified Hardware and Software System

Figure: Major system and SoC development tasks

The Solution: System Development Suite To alleviate these design challenges, look no further than the Cadence® System Development Suite. The suite reduces system integration time by up to 50% by accelerating system design, IP, and SoC verification as well as bring-up with a set of connected platforms for concurrent hardware/software development. Its technologies span the entire design cycle, across early software development, IP design and verification, subsystem and SoC verification, netlist validation, hardware/software integration and validation, and system and silicon validation. The suite is open for third-party integration, and supports industry standards and multiple levels of design abstraction. It allows easy migration among the platforms and between hardware/software domains. And it can scale to meet performance, capacity, and volume needs as they expand. The System Development Suite is built on market-leading platforms from Cadence: Many of these technologies have been applied to various customer challenges, including but not limited to: The System Development Suite technologies and methodologies, along with ongoing and expanding support for industry standards, have been effectively applied to a multitude of customer challenges, and are further augmented by our ecosystem partners, both on system and verification.
Early Software Development Key requirements of pre-silicon early software development—using models, ready register-transfer level (RTL), or prototypes of the underlying hardware prior to its readiness—are execution speed, software debug efficiency, and early availability.
  • Virtual Prototyping – The Virtual System Platform (VSP) enables fast execution and debug of the entire software stack on an early hardware model, including software driver validation on an accurate RTL model of the IP.
  • Early OS Bring-up – Palladium® Hybrid solution integrates a high-performance transaction-level model of the CPU subsystem running on Cadence® Virtual System Platform (VSP) with RTL for the rest of the SoC running on the Palladium platform
  • FPGA-Based Prototyping – Our next-generation Protium™ rapid prototyping platform is ideal for early, pre-silicon software development, throughput regressions, and high-performance system validation. The platform accelerates firmware and driver development, as well as early deployment of IP design kits to the IP end user.
IP Design and Verification Key requirements of IP and cluster design, integration, and verification are hardware debug efficiency, regression simulation bandwidth, and fast time to debug.

  • Transaction-Level Modeling-Driven Design and Verification — The TLM D&V Methodology provides higher abstraction design and verification doubles turnaround time.
  • High-Level Synthesis — Stratus HLS lets you quickly design and verify high-quality RTL implementations from abstract SystemC, C, or C++ models, delivering up to 10X better productivity than traditional RTL design and reducing the IP development cycle from months to weeks
  • Formal Analysis—JasperGold® Apps enable RTL block verification months earlier than with simulation, and speed time-to-design closure with early error detection, analysis, and pinpoint debug
  • Verification Planning and Management — The Incisive vManager solution automates visualization, analysis, and reporting of the functional verification process using metric-driven verification (MDV).
  • Metric-driven verification methodology—MDV methodology provides a data-driven decision-making and prescriptive methodology to improve verification productivity, predictability, and quality.
  • Assertion-Based Verification—ABV methodology enables earlier IP verification, faster and easier bug detection and correction, and more comprehensive MDV and debug, all across formal and dynamic tools.
  • Simulation—The Incisive Enterprise Simulator provides optimized performance for regression simulation driven from UVM, eRM, OVM, and mixed-language verification environments.
  • Debug Analysis—Indago Debug Platform and SimVision Debug provide a multi-language environment, with “interactive” post-process capabilities, saving significant debugging time for UVM, transaction analysis, waveforms, etc. The Indago Debug Platform, which applies Big Data capture and automated root-cause analysis, includes three built-in debug apps: Indago Debug Analyzer, Indago Embedded Software Debug, and Indago Protocol Debug.
  • Mixed-Signal Verification—The digital mixed-signal (DMS) option enables creation and validation of digital real-number models for analog blocks for mixed-signal designs.
  • VIP—The Verification IP Catalog speeds the verification of blocks that communicate via standard interface such as USB, PCI Express, AMBA AXI, etc.
SoC/Subsystem Integration and Verification Key requirements of SoC integration and verification—including functionality, compliance, power, performance, etc.—are hardware/software debug efficiency, multi-language verification, low power, mixed signal, fast time to debug, and execution speed.

  • Verification Planning and Management—Incisive® vManager solution provides hierarchical verification technology for multiple IPs, interconnects, hardware/software, and plans to improve management productivity and visibility.
  • Simulation—Incisive Enterprise Simulator and Incisive Enterprise Specman® Elite Testbench deliver high-performance simulation for integrated IEEE low-power, mixed-signal, digital mixed-signal, and digital systems on chip (SoCs) driven by e, SystemVerilog, and SystemC testbenches.
  • Targeted Formal-Based Verification—JasperGold® Apps accelerate SoC verification closure by leveraging formal technologies to efficiently complete specific verification tasks not easily handled by dynamic verification alone
  • Debug Analysis—Indago Debug Platform and SimVision Debug provide an integrated environment for mixed signal, low power, hardware/software co-debug, multi-chip SoC simulations, acceleration/emulation, VIP, and VIP protocol debug
  • VIP—The Verification IP Catalog and accelerated VIP components send and receive traffic from multiple standard interfaces to verify control and data flow across an SoC.
  • Simulation Acceleration and Emulation—Palladium® XP series speeds up design verification and regressions by order(s) of magnitude.
  • Low-Power Verification and Analysis—Incisive and Encounter® Conformal® Low-Power verification and Palladium Dynamic Power Analysis enable designers to efficiently verify implementation of low-power schemes and analyze power-switching activity for peak and average power.
  • Mixed-Signal Verification—The digital mixed-signal (DMS) option leverages digital real-number models for analog blocks to increase mixed-signal simulation performance, and enables digital verification methodologies for full-chip mixed-signal SoCs.
Hardware/Software Validation Key requirements of hardware/software integration and system validation—including software bring-up on top of the accurate hardware—are execution speed, hardware/software debug efficiency, fast time to debug, and appropriate capacity to execute the full design.

  • Emulation — Palladium® Z1 and Palladium XP series enables pre-silicon hardware/software integration validation and hardware-dependent software bring-up, interfacing full-speed device/system to a design running at emulation speed to ensure correct in-system behavior
  • Early OS Bring-Up – Palladium Hybrid solution integrates a high-performance transaction-level model of the CPU subsystem running on Cadence® Virtual System Platform (VSP) with register-transfer level (RTL) for the rest of the SoC running on the Palladium platform
  • Accelerated system integration: The next-generation Protium™ rapid prototyping platform accelerates system integration time by providing a high-performance, cycle-accurate, pre-silicon hardware implementation of the SoC
Gate-Level Validation Key requirements of validation of gate-level-view hardware, addressing timing closure, test, etc. are execution speed and accuracy for both simulated and hardware accelerated techniques.

  • Gate-Level Simulation: Incisive® Enterprise Simulator reduces the time to signoff with high accuracy, performance, and capacity for massive DFT, timed, and untimed gate-level simulations.
  • Gate-Level Emulation: Palladium Z1 and Palladium XP series enables gate-level netlist validation, including test and power logic, running at full acceleration/emulation speeds.
System and Silicon Validation Key requirements of validation of the integrated offering—with the bulk of it done post-silicon, aided by development technologies for debug and analysis—are a full system-environment to reproduce silicon tests in a visible debug environment with appropriate capacity and speed to execute full system operation.

  • Emulation — Palladium® XP series helps reproduce and correct errors found in post-silicon debug.
  • Early OS Bring-up – Palladium Hybrid solution integrates a high-performance transaction-level model of the CPU subsystem running on Cadence® Virtual System Platform (VSP) with register-transfer level (RTL) for the rest of the SoC running on the Palladium platform.
  • Virtual Prototyping — The Virtual System Platform (VSP) enables development of post-silicon test scenarios on virtual models while the RTL of the DUT is still in development.