Automating IP Creation and Reuse, Accelerating System Integration
Today’s SoC flows are under extreme pressure to meet the demands of product teams. In just the last ten years, Moore’s Law has driven SoCs to grow by more than 32x in complexity, while IC design productivity has less than doubled in the same period. However, by leveraging the Cadence System Development Solution, today’s advanced engineering teams are managing to work both smarter and faster.
By creating TLM IP as their “golden” source, design teams are accelerating IP creation and reuse, and reducing the time and effort spent on behavioral/functional verification. The ability to thoroughly explore and verify architectural choices long before implementation virtually eliminates expensive design iterations. Additionally, by creating IP transaction-level models using industry-standard SystemC, designers can readily use them not only for hardware/software co-verification but also for early software development using commonly available virtual platforms.
Nonetheless, final system integration and validation still happens at the RTL phase. This represents the “moment of truth” where engineers decide if a system is ready for (costly) physical implementation and manufacturing, or will require a (costly) re-spin. To contend with these challenges, advanced engineering teams rely on a combination of technologies for system planning and management, metric- and coverage-driven verification, hardware-software co-verification, and high-throughput emulation. Working in concert, these technologies give engineers the confidence they need in order to signoff designs for implementation and production.
System development is a complex, enterprise-level activity, requiring engineers to work at multiple levels, across multiple disciplines. To contend with this reality, the Cadence System Development Solution comprises four flows, each focused on a distinct set of challenges.
Cadence system development flows improve predictability, productivity,
quality, and power
- System Planning and Management flow: Building on the Cadence Incisive® Enterprise Manager and Chip Planning System, this flow automates the process of estimating chip feasibility, cost and performance prior to design, and then tracks the progress of an evolving system design against its functional, performance, and schedule objectives simultaneously. The result is higher predictability of R&D costs, schedule and deliverables, enabling companies to keep R&D resources allocated where they maximize company ROI.
- TLM-driven Design and Verification flow: Designed to address the “next-frontier” of SoC design, this comprehensive flow uniquely combines Cadence C-to-Silicon Compiler, next-generation high-level synthesis (based on industry-standard SystemC) and TLM Metric Driven Verification (based on industry-standard OVM) to ensure faster creation of reusable Design IP/Verification IP that engineers can integrate with other hardware and software, prior to RTL. Adopting a TLM-driven flow for creating/verifying new IP enables companies to dramatically increase both the productivity and leverage of their R&D, IP and VIP investments.
- System Verification and Validation flow: Building on Cadence Incisive Palladium® and Xtreme® technologies, SystemC simulation and Incisive Software Extensions, this flow lets engineers stress and validate their fully integrated system in scalable, realistic verification environments, thereby ensuring high quality and faster time to market. By making use of these capabilities, design and verification teams can rapidly bring up, verify, validate, debug, and turn around both the hardware and embedded software within their designs. At the conclusion of this process, the full SoC (hardware and software) can be brought up quickly as first silicon arrives.
- Power Aware System Development flow: The largest power savings come from making design decisions above RTL. Tradeoffs at the system architecture and block micro-architecture levels deliver much greater impact than those made at the logic/circuit and device/technology level. This flow combines tools for chip planning, next-generation high-level synthesis and dynamic power analysis to enable designers to set chip-level power constraints, explore IP-level micro-architectures, and dynamically analyze power consumption while running application software under real-world conditions. It supports the popular CPF standard, and enables designers to deliver systems with the lowest power for given cost and performance constraints.