Instead of regarding IP as isolated “component blocks,” Cadence delivers an IP stack that includes bare-metal software as well as hardware IP. Bare-metal software refers to everything below the operating system layer, the most prominent feature being device drivers. The IP stack also includes verification IP (VIP) that validates IP functionality and integration. Finally, the IP stack includes hard macros with fixed layouts along with synthesizable IP and a complete set of design constraints.
Characteristics of integration-optimized IP:
- Functionality is well-defined and documented
- Source, synthesis, and implementation packages are provided for integration
- Silicon-validated IP is available with characterization data
- IP meets documented quality guidelines
- IP blocks are parameterized
- IP stacks come with design constraints
- Test platform for IP comes with a complete verification environment for hardware and drivers
- Deliverables include all necessary scripts, guidelines, checklists, and documentation
Examples of Cadence integration-optimized IP:
For additional IP solutions, please contact Cadence.
To complement integration-optimized IP, component IP provides both common and high-performance IP that can be utilized in many different designs. Component IP is of high quality, has a well-defined set of deliverables, and works well in any SoC design environment.
Component IP is categorized into mixed-signal foundational IP, examples of which include analog front ends (AFEs), digital-to-analog converters (DACs), and analog-to-digital converters (ADCs). Peripheral IP examples include CODECS and low-speed interfaces such as SDIO and I2C. Security IP examples include coding algorithms such as AES and DES, hashing, and random number generation.
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