High-volume, highly integrated, ultra–low-power SoCs designed at advanced nodes (65nm and below) have strict timing, power, and area requirements coupled with aggressive design schedules. As these design risks increase and push the envelope of conventional methodologies, the cost of developing next-generation mixed-signal SoCs can be more than $100M.
Cadence® design, verification, and implementation platforms provide integrated, interoperable flows and innovative methodologies that help customers achieve Gigahertz speed, ultra low power, high yield, and reliability objectives.