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 Mixed-Signal Verification 

  • Metric-Driven Verification
  • Mixed-signal Simulation
  • Behavioral Modeling
  • Universal Verification Methodology
Universal Verification Methodology The traditional mixed-signal verification flow has so far been based on keeping the analog and digital portions of the design separate and verified independently in their respective design environments. Current mixed-signal designs are complex with mixed-signal intellectual property (IP) embedded in the digital hierarchy and vice versa.

Today’s mixed-signal designs have multiple feedback loops through analog and digital domains. The “black box” approach is not possible anymore for top-level verification. The new world is a complex, multilayered fusion of the two disciplines, where the boundaries are getting fuzzy and the interactions are complex and, at best, poorly modeled. This requires an integrated mixed-signal environment to address performance and reliability problems.

Top-level verification is one of the most critical challenges in mixed-signal verification. Cadence offers an integrated mixed-signal verification environment that ensures the reliability of the mixed-signal verification results.

Cadence’s core simulation products, such as the Spectre®, Virtuoso® Accelerated Parallel Simulator, Virtuoso UltraSim, Virtuoso Multi-Mode Simulation, and Incisive® families, provide high performance, an integrated engine, and multi-language support for mixed-signal design verification.

Cadence’s schematic model generation and analog mixed-signal design and model verification platform environment provides an automated and verifiable comprehensive flow for efficient and accurate analog behavioral modeling and verification.

With the mixed-signal simulation and behavioral modeling and verification capability, Cadence’s solution brings a metric-driven verification approach to digital-centric mixed-signal designs, providing scalability and high performance to full-chip SoC verification.
Flow Benefits
  • Improves time to market
  • Ensures the SoC meets the spec with overnight mixed-signal regression runs
  • Ensures product quality
  • Reduces re-spins
  • Leverages high-performance, real-number modeling
  • Performs top-level, metric-driven mixed-signal SoC verification
  • Finds and helps fix errors much earlier in the design cycle by performing full-chip functional verification
  • Boosts productivity
  • Eliminates convergence issues with digital-speed performance
  • Easily and accurately ports models between Virtuoso and Incisive environments
  • Enables top-level SoC verification
  • Supports real number models using System Verilog IEEE P1800-2012 standard
Flow Components
Behavioral Modeling With increasing complexity of today’s mixed-signal designs, top-level full-chip verification has become the biggest challenge in bringing the chips into production. The digital portion of designs has embraced the metric-driven verification approach and has a standardized flow for generation and tracking of verification coverage. However, top-level verification of digital-centric mixed-signal design requires verifying the analog portion of the chip in conjunction with digital portions of the chip.

Mixed-signal simulators have helped solve the problem by supporting behavioral models of the analog portion of the designs using Verilog-A, Verilog-AMS and Verilog-AMS with real-number models. But, the biggest bottleneck exists in generating the behavioral models.

Cadence’s schematic model generator (SMG) is tightly integrated into the Virtuoso® environment and enables the generation of analog/mixed-signal behavioral models using a schematic-like representation of the behavioral model. The schematic view is then processed to generate the behavioral model in Verilog-AMS and/or Verilog-AMS with wreal. With this approach, behavioral modeling becomes easier to comprehend and manage compared to manual textual entry process.

The SMG is easy to use and uses the Virtuoso Schematic Editor to build the blocks that can be placed, wired, and calibrated. The model schematic can be reused, shared, configured, and easily maintained. The graphical representation of design functionality makes the modeling process very transparent and understandable for analog circuit designers and verification engineers.

Cadence’s Analog Mixed Signal Design and ModelValidation (amsDmv) application provides an integrated model validation solution to verify behavioral models against the reference analog design using simulation. amsDmv is integrated with the Virtuoso GUI flow to provide an automated process for pass-fail output and reports, as well as extensive debugging capabilities to validate the behavioral models.

The tight integration of the SMG and amsDmv with the Virtuoso design environment helps to bring metric-driven verfication to mixed-signal designs.
  • Easy to use (schematic/GUI-based)
  • Reusable model schematic
  • Model generation to create a standard text model
  • Improved and consistent model quality
  • Automated flow
  • Close integration with the Virtuoso design platform
  • Easy-to-use GUI-based setup
  • Support for Verilog-AMS, VHDL-AMS, SystemC, and wreal models
  • Easy-to-read pass/fail reports with analog and digital waveform results
Mixed-signal Simulation Cadence’s mixed-signal simulation technology portfolio includes a broad portfolio of simulators ranging from analog solvers to mixed-signal simulators and digital simulators. Our simulation technology caters to both digital-centric and analog-centric mixed-signal designs.

Cadence’s Virtuoso® AMS Designer provides an advanced mixed-signal simulation solution for addressing design and verification of analog, RF, memory, custom digital and mixed-signal intellectual property (IP) and systems on chip (SoCs). This unified solution with a single simulation executable provides appropriate simulation technology to different levels of design abstraction. The key simulation technologies included are Virtuoso Spectre Circuit simulator, Virtuoso Accelerated Parallel Simulator (APS), and Virtuoso UltraSim Full-Chip Simulator. These simulators support common syntax and device models and are fully integrated into the industry-leading Virtuoso full-custom environment and Cadence Incisive® functional verification platform.

Virtuoso AMS Designer is a mixed-signal simulation solution for the design and verification of analog, RF, memory, and mixed-signal SoCs in an analog-centric flow. It is tightly integrated with the Virtuoso full-custom environment for mixed-signal design and verification and with the Cadence Incisive functional verification platform for mixed-signal verification within the digital verification environment.

Closely integrated with the industry-leading Virtuoso Analog Design Environment, Virtuoso AMS Designer provides a true mixed-signal simulation environment. Virtuoso AMS Designer supports the whole language spectrum, ranging from SPICE to Verilog, providing superior performance and methodology scalability.  

Along with Incisive Enterprise Simulator, Cadence’s mixed-signal verification flow brings metric-driven verification for digital-centric mixed-signal designs by leveraging real number models (RNM), including the latest SystemVerilog IEEE 1800-2012 standard. This allows the top-level mixed-signal verification to use the digital solver, avoiding the slower analog simulation and thus enabling intensive verification of mixed-signal design in short period of time. RNM support opens the possibility of linkage with Incisive Enterprise Manager, bringing advanced verification technologies such as assertion-based verification and open verification methodology flow, which bridges the gap between analog and digital verification.

Improves time to market
  • Overnight mixed-signal regression runs ensure the chip meets the spec
  • Ensures product quality
  • Supports the latest SV-RNM standard – IEEE 1800 SV-2012
Reduces re-spins
  • Leverages high-performance, real number modeling
  • Performs SoC top-level mixed-signal verification
  • Finds and fixes errors much earlier in the design cycle by performing full-chip functional verification
Boosts productivity
  • Eliminates convergence issues with digital-speed performance
  • Easily and accurately ports models between Virtuoso and Incisive environments
  • Achieves top-level verification
Product Integration
Metric-Driven Verification Digital designs have had the benefits of a metric-driven verification flow for quite some time. With a metric-driven verification flow, verification plans are tailored based on the given specifications, with proper tracking of progress and the ability to determine the exact verification coverage levels. The methodology thus provides structure and confidence for verification engineers to determine the quality of the design. However, analog designs are verified using an analog solver-based approach that is time-consuming and error prone. This process is tedious in terms of setup, and costs precious CPU time to verify.

With complex mixed-signal designs, verifying the analog portion of the design in conjunction with the digital portion is the biggest challenge, from a verification standpoint. Mixed-signal simulators and environments such as Cadence’s Virtuoso® AMS Designer and Incisive® simulators have evolved to support true mixed-signal simulations. In true mixed-signal simulations, analog and digital portions use the respective simulation environment, event-based digital simulators, and analog solvers to verify the complete mixed-signal systems on chip (SoCs). But, the biggest bottleneck in verifying top-level mixed-signal SoCs is the slow analog simulations.

Cadence’s mixed-signal metric-driven verification flow addresses top-level mixed-signal SoC verification in a seamless and easy-to-use flow using real-number models. The flow helps to bring assertion-based verification to mixed-signal designs. This is made possible by the automated analog behavioral modeling supported by the Virtuoso schematic model generator (SMG) product and validation flow using amsDev. Assertion-based flows can be used in top-level mixed-signal designs to capture specifications and design intent in an executable form, bringing formal analysis for exhaustive verification of analog interfaces .

Cadence’s Incisive verification technologies, consisting of Incisive Formal Verifier, Incisive Enterprise Verifier, Incisive Enterprise Simulators along with Cadence Palladium® accelerators/emulators, support industry-standard assertions such as IEEE 1850 Property Specification Language (PSL) assertions in SystemVerilog, Verilog®, VHDL, SystemC® code and IEEE 1647 e verification language assertions in e code. Incisive Assertion Library supports the Accelerra Open Verifcation Solution. Mixed-signal verification management is done using Incisive Enterprise Manager and Planner, which provides extended language and simulation support along with automated verification management.
  • Improved verification planning resulting in higher quality
  • Metrics analysis and reporting that increase schedule predictability
  • Failure/metrics analysis and job automation that boost overall team productivity
Flow Components