Mixed-signal IP design is more complex than ever before, resulting in a new set of issues that expose weaknesses in design skills, tools, and flows. Today’s SoCs tax IP creators with meeting aggressive functionality, performance, power, yield, and area specifications. To streamline the development and integration of mixed-signal IP into these SoCs, engineers require additional and optimized design tools, methodologies and flows.
Cadence provides integrated flows with interoperable tools and specialized methodologies that target mixed-signal IP creation challenges. At the core of these technologies is market-leading Virtuoso® 6.1 custom design and Multi-Mode Simulation products, which are easy to adopt and boost productivity straight away. Interoperability between Virtuoso tools and Encounter® digital design and implementation technologies optimize the creation of both analog-intensive and digital-intensive chips to eliminate design iterations, spare time, and reduce cost.