Today’s mixed-signal ICs are highly integrated, multi-domain, cost-sensitive chips typically manufactured on mature process nodes (90nm and above). To achieve reliability and overhead objectives, early consideration of packaging and packaging effects are critical.
Virtuoso® platform, Multi-Mode Simulation, Encounter® platform, and Allegro® system-in-package (SiP) technologies provide end-to-end verification and implementation solutions that enable new IC co-design flows and methodologies.