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 Mixed-Signal Solution 

ams
Thomas Moerth
ams

Engineers at ams AG were frustrated at how long it was taking to verify their mixed-signal designs. If there wasn't enough time in the schedule, the trade-off was to not verify everything, but risk having chips that didn't work as expected. Knowing that they had reached their limits with the hardware, the ams team turned to software for an answer. In this short video, Thomas Moerth, the company's manager of Design Support, Full-Service Foundry, talks about how Cadence® Virtuoso® AMS Designer helped ams complete 2X the number of simulations as was previously possible and how Cadence Spectre® Extensive Partitioning Simulator helped boost simulation speed by 10X.


 
IBM
Sangtae Bae
IBM

Transistor-Level Reliability Analysis for Advanced Node Description: Sangtae Bae, an analog/mixed-signal circuit designer at IBM, designs high-speed interfaces for IBM's server chips. Bae and his team needed a method to verify circuits will operate in silicon, reliably well over expected life of products. In this 4-minute video, Bae explains how reliability simulation in Cadence® Spectre® Accelerated Parallel Simulator (APS) ran from Cadence Virtuoso® Analog Design Environment (ADE) helped IBM perform reliability analysis efficiently and get to market faster with its server chips.


 
PMC
Vivekanand Malkane
PMC

Engineers at PMC were frustrated with their slow, manual process for verifying analog IP and developing functional models. To automate its processes, the company implemented Cadence® Virtuoso® Schematic Editor and a SystemVerilog testbench. In this video, Vivekanand Malkane, technical manager of the mixed-signal verification team at PMC, talks about how much more efficient the team's verification process is.


 
STMicroelectronics
Livio Frantantonio
STMicroelectronics

STMicroelectronics relies on mixed-signal solutions for its Smart Power Technologies. As Livio Frantantonio explains in this video, STMicro needed to increase productivity and quality of results while shortening its turnaround times. The company found its answer in Cadence's mixed-signal solutions, including Virtuoso® Mixed-Signal Flow. Watch this video to learn how STMicro benefited from using the Cadence Unified Mixed-Signal Methodology.


 
Ricoh
Business Challenges
  • Accelerate development cycle for multifunction printer ASICs
  • Automate verification management process
Design Challenges
  • Lack of effective solutions to avoid missing test cases
  • Need to minimize time spent capturing verification status before actual problem solving
Cadence Solutions
  • Incisive vManager solution
  • Incisive Enterprise Simulator
  • Metric-driven verification (MDV) methodology
Results
  • vManager solution addresses approximately 22% of the missing or incomplete test case issues
  • 2.5 months saved in data collection and reporting time
  • Ability to start resolving issues earlier in the design cycle
 Read full story»


 
Analog Devices
Eduard Raines
Analog Devices

Watch this video to learn how Analog Devices ramped up engineering productivity using ModGen tools in Cadence's Virtuoso® Layout Suite solution. CAD engineer Eduard Raines explains how his team replaced time-consuming manual processes with an automated solution to create custom programs for high performance, highly matched design structures.


 
Silicon Labs
Business Challenge
  • Ramp up the company’s product development capabilities
Design Challenge
  • Create and implement efficient design flow and methodology, supported by single toolset, for development of low-energy MCUs
Cadence Solution
  • Integrated mixed-signal, low-power RTLto-signoff flow based on Cadence Assura, Encounter, Incisive, and Virtuoso platforms
Results
  • Saved several months in development time for design flows
  • 20 months after the start-up of the company, the first 32-bit MCU (EFM32 Gecko) was launched, consuming only a quarter of the energy of competing products
  • Developed new 32-bit MCU in just 4 months, saving up to 8 months of effort due to innovative design methodology and focus on re-usability
 Read full story»


 
Analog Devices
Anthony Agrillo
Analog Devices

Anthony Agrillo, a layout engineer at Analog Devices, works with a team that needs to build small-scale, non-timing digital blocks to go with the analog blocks in their design. Frustrated at how long their manual process took, the team turned to the Cadence® Virtuoso® Custom Placer and Virtuoso Space-based Router in Cadence's Virtuoso Layout Suite. Watch the video to find out how much time the team is saving and how much more efficient their process is.


 
Allegro Microsystems
Steve Nedeau
Allegro Microsystems

Allegro Microsystems has small, custom digital blocks to implement. By hand, such designs were taking up to three days to complete. With the Virtuoso® Custom Placer and Virtuoso Space-based Router in Cadence's Virtuoso Layout Suite, Allegro cut that place-and-route time down to a less than a day and reduced its block size by 30%. Watch the video to hear what Steve Nedeau, senior IC layout engineer, says about how the tools have made his life easier.


 
STMicroelectronics
Preeti Kapoor
STMicroelectronics

At advanced process nodes, new challenges such as layout-dependent effects emerge. STMicroelectronics needed to address these challenges and automate its full custom analog layout flow. Watch this video to hear Preeti Kapoor, a design engineer at the company, talk about using design constraints (specifically, modgens) to create a faster and more accurate DRC clean design.


 
Micron Technology
David Paquet & Julie Sulisthio
Sr. CAD Manager & Sr. CAD Engineer at Micron Technology

Hear from David Paquet, Sr. CAD Manager and Julie Sulisthio, Sr. CAD Engineer from Micron Technology as they talk about the use of Physical Verification System Constraint Validator in conjunction with Virtuoso Constraint System to validate design intent and improve design quality.


 
TSMC
Maria Marced
TSMC Europe

Maria Marced, President of TSMC Europe, and Christian Malter, Director Technology Solutions, EMEA, Cadence, discuss how customers benefit from the collaboration between the two companies in the mixed-signal space.


 
ARM
Keith Clarke
VP for Embedded Processors at ARM

Keith Clarke, VP for Embedded Processors at ARM, talks about the importance of facilitating mixed-signal designs by partnering with companies such as Cadence, who can provide knowledge and expertise to the ecosystem.


 
Freescale Semiconductor
Angela Liang
Freescale Semiconductor

Hear from Angela Liang, Sr. Mixed-Signal Verification Engineer, at Freescale Semiconductor as she describes how they utilized the Cadence Low Power and Mixed-Signal Solution to verify the company’s Kinetis Microcontroller products targeted for automotive and internet-of-things applications.


 
S3
S3
Flavio Cali

Hear from Flavio Cali with S3 Group, as he highlights the user experience of Cadence Physical Verification System (PVS) for SoC design.


 
Saphyrion
Angelo Consoli
Saphyrion

Angelo Consoli, Managing Director at Saphyrion, details how they leverage the Cadence Virtuoso custom/analog flow and design services to develop ASICs High-End ground and space applications.


 
STMicroelectronics
Romain Feuillette
STMicroelectronics

Romain Feuillette, Team Leader at STMicroelectronics, talks about succeeding with the Cadence innovative Virtuoso custom/analog flow to meet aggressive roadmaps and improve productivity at all process nodes.


 
S3
Dermot Barry
S3

Dermot Barry, VP – Silicon Business Unit at S3, highlights how they leverage Cadence mixed-signal solutions to help their customers achieve business success through fast time to market and first time right silicon with the optimized power, performance and area.


 
X-Fab
X-Fab
Dr. Jens Kosch
Chief Technology Officer
Dr. Jens Kosch, CTO at X-Fab, highlights the use of the Cadence Mixed-Signal solution to help mutual customers with their designs.


 
Texas Instruments
Business Challenge
Short time-to-market window for complex mixed-signal design verification
Design Challenges
High-performance, ultra low-power features in close interaction with core analog functional blocks at the SoC level
High-volume product
Functional failures would lead to costly design iterations
Cadence Solutions
Digital-centric mixed-signal verification flow
Incisive Enterprise Simulator Digital/Mixed-Signal (DMS) Option
Incisive Enterprise Specman Elite Testbench
Incisive Enterprise Manager
Virtuoso AMS Designer with flexible analog simulation
Virtuoso Accelerated Parallel Simulator – XL
Customer Support
Results
300x faster verification vs. mixed-signal simulation at the transistor level
Improved time to market and product quality with mixed-signal regression runs
Fewer re-spins with high-performance, real-number modeling and top-level, metric-driven mixed-signal SoC verification
Earlier detection and correction of errors
10x cycle-time improvement in mixed-signal verification
 Read Full story»


 
Freescale Semiconductor
Design Challenges
Mixed-signal design with new flash technology and new ARM Cortex-M4 core
10 different power modes ranging from high-performance through very low leakage standby mode
Advanced techniques like innovative back-biasing scheme and multi-length gate libraries
Cadence Solution
Full low-power flow including power-aware simulation, synthesis and scan insertion, physical design and formal verification
 Read Full story»


 
LSI Corporation
Business Challenges
Establish a proven mixed-signal methodology to verify analog IP for a mixed-signal chip
Produce a high-quality product in a short time-to-market window
Design Challenges
Upgrade ad-hoc, manual verification methodology for analog IP
Leverage current, optimal verification flow for digital IP
Cadence Solutions
Incisive Enterprise Simulator
Incisive Enterprise Manager
Incisive Enterprise Specman Elite Testbench
Virtuoso AMS Designer
Virtuoso Schematic Editor
Virtuoso Analog Design Environment
Customer Support
Results
Established a methodology that can be extended to analog verification
Expanded analog design verification coverage and improved product quality
Met design and performance specifications
 Read Full story»


 
TowerJazz
Business Challenges
Time-to-market pressures
Rising development costs
Design Challenge
Product differentiation and customization for analog and mixed-signal specialty products
Cadence Solutions
Virtuoso unified custom/analog flow
Virtuoso Layout Suite
Virtuoso Analog Design Environment
Virtuoso AMS Designer
Virtuoso Spectre Circuit Simulator
Virtuoso Space-Based Router
Cadence QRC Extraction
Cadence Services
Results
Complete, customized offerings with a wide array of tools and functions
Lower development costs
Faster time to market
 Read Full story»


 
austriamicrosystems
Thomas Riener
austriamicrosystems

Thomas Riener, Sr. VP, General Manager Foundry Business at austriamicrosystems describes how they leverage the Cadence unified custom/analog flow to design the company’s analog IC products.


 
STMicroelectronics
Romain Feuillette
STMicroelectronics

Romain Feuillette, Team Leader at STMicroelectronics describes the benefits of using the Cadence Virtuoso-based custom/analog flow to enable faster time to market, higher productivity, and product innovation.


 
Siemens
Design Challenge
Build an all-encompassing chip-level verification plan over the entire functionality of the ASIC, including both hardware and software, that addresses real-life use cases and user scenarios
Reduce overall project time
Develop a flexible, trustworthy verification plan to stay on track, manage progress, and automate coverage collection to address unforeseen design changes
Integrate formal analysis technology into the verification flow

Cadence Solution
Cadence Incisive Enterprise Manager
Cadence Incisive Enterprise Specman Elite Testbench
Cadence Incisive Formal Verifier
Cadence Incisive Enterprise Simulator
 Read Full story»


 
Silicon Laboratories
Design Challenge
Full-chip verification was much too slow with regard to integrating the analog and digital content at the full chip level
Verification productivity must be improved by allowing users to begin the digital verification effort much sooner in the overall process

Cadence Solution
Cadence Incisive Enterprise Simulator running the Digital Mixed Signal option
Cadence Mixed-Signal Solution allows users to seamlessly connect Real Value Models to the digital content
 Read Full story»


 
Multigig
Design Challenge
Simulation of complex RF and mixed-signal designs
High-frequency, low-amplitude phase-locked loops (PLLs)

Cadence Solution
Fast and accurate design and simulation of RF blocks
Full-chip simulation and verification
 Read Full story »


 
Realtek
Design Challenge
Shorter design cycles
Simulation of larger, more complex mixed-signal designs

Cadence Solution
Large-capacity design and verification based on known database structures
Mixed-signal verification using FastSPICE technology
 Read Full story »


 
Teradyne
Design Challenge
Complex analog and mixed-signal SoC simulations
Wide variety of applications and test priorities

Cadence Solution
Token-based licensing model for flexible simulation solutions over a wide range of design verification requirements
Increased speed to market from a single testbench configuration directly integrated to the design process
 Read Full story »


 
Zmd
Design Challenge
Be first to market with an ultra low-power sub-1GHz RF transceiver for ZigBee technology
Augment internal analog design knowledge with digital expertise to meet aggressive timing constraints

Cadence Solution
Advanced clock-tree synthesis using Cadence First Encounter® silicon virtual prototyping
Stopped the calendar bleeding and achieved a predictable tapeout
 Read Full story »