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Mixed-Signal Solution 

Freescale Semiconductor
Anis Jarrar
Freescale Semiconductor
 Anis Jarrar, Principal Design Engineer, at Freescale Semiconductor describes how they utilized the Cadence Low-Power Solution to design and implement the complex Kinetis SoC.

Texas Instruments
Business Challenge
Short time-to-market window for complex mixed-signal design verification
Design Challenges
High-performance, ultra low-power features in close interaction with core analog functional blocks at the SoC level
High-volume product
Functional failures would lead to costly design iterations
Cadence Solutions
Digital-centric mixed-signal verification flow
Incisive Enterprise Simulator Digital/Mixed-Signal (DMS) Option
Incisive Enterprise Specman Elite Testbench
Incisive Enterprise Manager
Virtuoso AMS Designer with flexible analog simulation
Virtuoso Accelerated Parallel Simulator – XL
Customer Support
Results
300x faster verification vs. mixed-signal simulation at the transistor level
Improved time to market and product quality with mixed-signal regression runs
Fewer re-spins with high-performance, real-number modeling and top-level, metric-driven mixed-signal SoC verification
Earlier detection and correction of errors
10x cycle-time improvement in mixed-signal verification
 Read Full story»

Freescale Semiconductor
Design Challenges
Mixed-signal design with new flash technology and new ARM Cortex-M4 core
10 different power modes ranging from high-performance through very low leakage standby mode
Advanced techniques like innovative back-biasing scheme and multi-length gate libraries
Cadence Solution
Full low-power flow including power-aware simulation, synthesis and scan insertion, physical design and formal verification
 Read Full story»

LSI Corporation
Business Challenges
Establish a proven mixed-signal methodology to verify analog IP for a mixed-signal chip
Produce a high-quality product in a short time-to-market window
Design Challenges
Upgrade ad-hoc, manual verification methodology for analog IP
Leverage current, optimal verification flow for digital IP
Cadence Solutions
Incisive Enterprise Simulator
Incisive Enterprise Manager
Incisive Enterprise Specman Elite Testbench
Virtuoso AMS Designer
Virtuoso Schematic Editor
Virtuoso Analog Design Environment
Customer Support
Results
Established a methodology that can be extended to analog verification
Expanded analog design verification coverage and improved product quality
Met design and performance specifications
 Read Full story»

TowerJazz
Business Challenges
Time-to-market pressures
Rising development costs
Design Challenge
Product differentiation and customization for analog and mixed-signal specialty products
Cadence Solutions
Virtuoso unified custom/analog flow
Virtuoso Layout Suite
Virtuoso Analog Design Environment
Virtuoso AMS Designer
Virtuoso Spectre Circuit Simulator
Virtuoso Space-Based Router
Cadence QRC Extraction
Cadence Services
Results
Complete, customized offerings with a wide array of tools and functions
Lower development costs
Faster time to market
 Read Full story»

Siemens
Design Challenge
Build an all-encompassing chip-level verification plan over the entire functionality of the ASIC, including both hardware and software, that addresses real-life use cases and user scenarios
Reduce overall project time
Develop a flexible, trustworthy verification plan to stay on track, manage progress, and automate coverage collection to address unforeseen design changes
Integrate formal analysis technology into the verification flow

Cadence Solution
Cadence Incisive Enterprise Manager
Cadence Incisive Enterprise Specman Elite Testbench
Cadence Incisive Formal Verifier
Cadence Incisive Enterprise Simulator
 Read Full story»

Silicon Laboratories
Design Challenge
Full-chip verification was much too slow with regard to integrating the analog and digital content at the full chip level
Verification productivity must be improved by allowing users to begin the digital verification effort much sooner in the overall process

Cadence Solution
Cadence Incisive Enterprise Simulator running the Digital Mixed Signal option
Cadence Mixed-Signal Solution allows users to seamlessly connect Real Value Models to the digital content
 Read Full story»

Multigig
Design Challenge
Simulation of complex RF and mixed-signal designs
High-frequency, low-amplitude phase-locked loops (PLLs)

Cadence Solution
Fast and accurate design and simulation of RF blocks
Full-chip simulation and verification
 Read Full story »

Realtek
Design Challenge
Shorter design cycles
Simulation of larger, more complex mixed-signal designs

Cadence Solution
Large-capacity design and verification based on known database structures
Mixed-signal verification using FastSPICE technology
 Read Full story »

Teradyne
Design Challenge
Complex analog and mixed-signal SoC simulations
Wide variety of applications and test priorities

Cadence Solution
Token-based licensing model for flexible simulation solutions over a wide range of design verification requirements
Increased speed to market from a single testbench configuration directly integrated to the design process
 Read Full story »