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 Low-Power Solution 

  • Overview
  • Chip Planning
  • Micro-architecture
  • Closed-loop Verification
  • Logic Design and Test
  • Low Power Validation
  • Digital & Mixed-signal Implementation
  • Estimation & Analysis
The Cadence Low-Power Solution provides power estimation and analysis at appropriate stages of the design flow, delivering quantitative feedback on whether design decisions will meet the power specification. This offers designers a convergent design process with front-to-back power predictability.

Chip planning Cadence chip planning solutions provide desktop estimation, leveraging power data from the vast database; and they provide enterprise-class solutions, which additionally manage and leverage in-house IP data.

Cadence InCyte Chip Estimator Learn more »
Cadence Chip Planning System Learn more »

Logic synthesis Encounter® RTL Compiler provides accurate power estimation for RTL and gate level, with options for probabilistic or real switching activity, options to explore clock gating, prototype clock-tree implementation, and options to introduce other physical implementation information along the way. RTL Compiler is also embedded under-the-hood in C-to-Silicon Compiler to provide rapid architectural exploration, enabling quick estimation from the SystemC™ transaction level.

Dynamic power analysis Accurate full-chip power analysis requires deep activity vectors that are fully representative of real system modes, often involving system software. It also requires accurate characterization of the design. In traditional flows, it is difficult to execute enough vectors at lower abstraction levels where characterization is adequate. Often, true analysis is only possible when first silicon is received, which is a huge risk in terms of schedule, cost, and quality.

Palladium® Dynamic Power Analysis (DPA) solves this problem by rapidly executing real system modes with real system software to create the activity data. This data is then applied to the design synthesized to the real target library, providing accurate estimation.

Signoff power analysis Cadence signoff-certified engines—Voltus™ IC Power Integrity Solution and Virtuoso Power System for custom/mixed-signal designs—provide accurate power analysis correlated with silicon, power rail integrity analysis, and IR-drop and thermal analysis.
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Functional verification must be power-aware While the designer sees a few simple power domains and focuses on the legal power modes, the verification engineer must demonstrate that the design responds correctly to a larger set of randomized operating sequences. And where the designer can be satisfied with a directed test for each state of each domain, the verification engineer needs to make every functional test power aware, often requiring thousands of tests, to prevent bugs from escaping into the silicon. The ability to construct tests that exercise the design in various modes, execute the tests, measure the response, analyze results, and check coverage against a verification plan is collectively known as closed-loop verification.

Incisive low-power verification technologies Accuracy and speed are the foundation of closed-loop verification, which, for low-power designs, means modeling silicon in ways not contemplated in Verilog or VHDL. Cadence® Incisive® verification technologies address this with native support for the Common Power Format (CPF) to verify low-power intent with no disruption or modification to the functional verification environment.

Incisive Enterprise Simulator models low-power component behavior, such as state retention registers and isolators, from the power intent file, unless such components are already instantiated in the design under test (DUT). The simulator correctly corrupts functional logic in the power-off state. Full power-aware debug tools allow you to verify that domains in the “off” state do not corrupt those in the “on” state, and that domains return to the on state correctly upon restoration of power. Assertions are generated to automate the creation of power-aware testbenches, and a low-power plan is generated from the power intent file to enable closed-loop verification. Close integration with Virtuoso® AMS Designer provides power-aware mixed-signal verification. Low-power functional verification metrics are collected and reported, and an easy-to-use graphical verification environment allows for quick debugging of issues related to errors in the low-power design intent. Learn more »

Palladium® Z1 and the Palladium XP series support CPF/UPF/IEEE 1801 for power-aware emulation. Customers have been able to verify correct operation of their power shutoff domains at up to 1,000X the speed of simulation.

Formal low-power verification and equivalence checking For rigorous closed-loop verification, Cadence recommends a mix of simulation-based and formal verification techniques. Conformal® Low Power is the industry’s leading formal verification solution for power-aware functional, structural, and equivalence checks. You can use these checks early and often to verify power intent files for quality and completeness, to check the power cells in your standard cell library, and for correct power-aware synthesis—at every stage of physical design. Learn more »
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Explore power, performance, and area with high-level synthesis Macro-architectural decisions such as the compute sub-system, memory architecture and other major IP choices represent typically 70-80% of the design content in today’s complex SoCs. These choices are covered in the Chip Planning and IP section. The remaining 20-30% represents the new design content – functional blocks which will provide new capabilities that will differentiate the SoC’s design.

Cadence C-to-Silicon Compiler High level synthesis products such as C-to-Silicon Compiler take high level descriptions of functional blocks, in the form of C/C++ algorithms with SystemC™ transaction-level models, to a Verilog implementation where power, performance and area (PPA) can be more accurately assessed. Typically, there are many different micro-architectures possible for implementing these blocks—different combinations of serial vs. parallel, resource sharing, pipelining, data storage, scheduling—which leads to a large 3D space of possible implementations with different PPA characteristics.

Using C-to-Silicon Compiler, designers can rapidly explore multiple micro-architectures for a functional block (a JPEG example is shown in the graphs), and then generate implementation-ready RTL for the particular micro-architecture that delivers the desired balance of PPA for their product. The JPEG example shows many different runs exploring a broad space. Designers can then take the RTL downstream to assess the power efficiency with even more accuracy in RTL synthesis. Because this micro-architecture exploration can be done graphically within C-to-Silicon Compiler at a high level of abstraction, designers can quickly converge on a micro-architecture for their unique design requirements, whether it’s ultra-low power, high performance, or a balance of each. This is far more exploration in a shorter time than could practically be accomplished by writing and re-rewriting RTL micro-architectures manually. Learn more »

Encounter RTL Compiler “under the hood” Encounter® RTL Compiler technology is embedded in C-to-Silicon Compiler to deliver consistently accurate power, timing and area information during the entire high-level synthesis process, resulting in RTL that attains design closure more predictably on your PPA goals for all types of designs.
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Early macro-architecture decisions hugely influence power Decisions made during the architectural phase of the IC design cycle have a major impact on the ultimate size, power consumption, performance, and cost of the final chip. Early IP choices can have the greatest effect on the chip’s final power, but the result of those choices can be difficult to measure until later.

Cadence Design IP focuses on the memory and storage subsystem, as well as high-performance interfaces, and is implemented utilizing our extensive expertise in and technologies for low-power design. Learn more »

Cadence IP Alliances provide processor IP choices from partners such as ARM and MIPS to cover a multitude of points in the power-performance space. Learn more »

Chip planning Availability of these power-efficient IP choices, plus the means to assess the IP in the context of alternative power architectures early in the design flow, is critical to success. Cadence chip planning solutions enable design teams to balance their often-conflicting goals by performing rapid what-if analysis and optimizing design specifications to achieve an optimal chip plan. With power architecture planning, designers can assess power consumption, leakage, and component overhead cost of using common power-saving techniques.

Cadence InCyte Chip Estimator Provides an architectural exploration environment where users can quantify and compare a vast number of chip implementation options to balance technical and economic goals. Learn more »

Cadence Chip Planning System An enterprise-class IC planning and IP reuse environment designed for larger, global organizations. Provides support for estimation with custom IP and manufacturing processes. Features a comprehensive IP reuse management system. Learn more »

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Low-power implementation Physical implementation is an integral part of the Low-Power Solution. Leveraging the same pervasive Common Power Format (CPF) design intent used throughout the Low-Power Solution, you benefit from fully automated, correct-by-construction low-power implementation that can turn your advanced power-efficient design into reality. The low-power design capabilities in Encounter® Digital Implementation System support all major design techniques such as power shutoff (PSO), multi-supply voltage (MSV), dynamic voltage and frequency scaling (DVFS), substrate biasing, and more. These capabilities are available use with floor planning, or full digital and mixed-signal implementation solutions, and are fully supported by integrated sign-off engines for power rail integrity and power analysis.

Encounter Digital Implementation System Delivers a complete solution for giga-gate/GHz, low-power, and mixed-signal designs at advanced and mainstream process nodes in a single, scalable multi-CPU–enabled design environment. Learn more »

Virtuoso Digital Implementation Provides a complete synthesis/place-and-route system for small digital block implementation in the context of a schematic-driven, mixed-signal design methodology. Learn more »

Voltus IC Power Integrity Solution Provides consistent and convergent power and power rail integrity analysis and optimization across the design and implementation flow, from power planning through signoff. Front-end logic designers benefit from high-quality, early analysis with ease of use, while back-end physical designers are assured of comprehensive signoff analysis and silicon correlation. Learn more »

Virtuoso Power System Enables custom design teams to efficiently analyze power and signal integrity for all designs implemented using a custom methodology. Learn more »

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The industry’s most comprehensive, rigorous, and trusted solution for low-power validation Implementing aggressive power reduction techniques affects the functionality of a design, and it causes logic and structural transformations during implementation. Cadence low-power validation technology delivers early validation of power intent specifications using the production-proven Common Power Format (CPF). It also ensures proper implementation of power-saving logic and structures throughout the design flow.

Power intent creation and validation Encounter® Conformal® Low Power enables the creation and validation of power intent in context of the design. It combines low-power equivalence checking with structural and functional checks to enable full-chip verification of power-efficient designs. Learn more »

Low-power validation for mixed-signal designs Virtuoso® Schematic Editor has recently been extended to enable and assist analog/mixed-signal or custom designers with exporting power intent, in the form of a CPF macro model, for blocks or full designs. This capability allows complete mixed-signal designs to benefit from Conformal Low Power’s rigorous validation. Learn more »

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Four facets of a leading low-power synthesis solution
Low-power optimization is the ability to synthesize logic that meets power, area, and timing constraints while also addressing testability. While other tools optimize for timing first, then attempt to fix that solution for power, Encounter® RTL Compiler uses algorithms that find the optimal logic structure to meet all constraints in a single pass, resulting in higher quality of silicon (QoS). RTL Compiler further optimizes power using techniques such as advanced clock gating, multi-bit cell inference, and multi-voltage threshold optimization.

Power domain-aware synthesis automatically infers components (such as state retention registers, isolators, and level shifters), which correctly implement the power intent. RTL Compiler implements a wide range of advanced low-power techniques, such as power shutoff (PSO), state retention power gating (SRPG), and multi-supply voltage (MSV), and handles complex hierarchies of power domains. Unlike other solutions, RTL Compiler ensures that logic restructuring and gate-level optimization respect power-domain boundaries without invalidating power intent rules.

Accurate power analysis is required for predictability that the power specification will be met. Appropriate accuracy for each stage of the design flow requires a proven synthesis engine with options for probabilistic or real switching activity, clock-gating exploration, prototype clock-tree implementation, and the introduction of other physical implementation information along the way. RTL Compiler provides these capabilities for RTL power estimation and gate-level power analysis.

Power-aware test is critical for today’s advanced low-power designs. Design-for-test (DFT) tools must be power-aware, ensuring that power management can be controlled during test mode and that the test structures themselves do not invalidate power intent rules. Encounter DFT Architect supports all of this and integrates seamlessly with RTL Compiler. Learn more »

Power consumption in test mode is another serious issue. Power dissipated during test mode can be many times that of normal operating modes. Test mode must not exceed the design parameters of the power rails or thermally stress the chip. Encounter True-Time ATPG achieves this by managing toggle rates during test pattern generation, without unduly extending pattern length and thus test time. Learn more »
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Power: a primary design constraint and a product differentiator Power consumption affects the designer’s ability to differentiate a product based on features, cost, performance, time to market, and even reliability. For mobile equipment, the explosion of applications leads to skyrocketing performance demands, in turn requiring innovative energy management. For data centers, where cooling represents a large proportion of overhead, power density management is critical to reduce cooling costs and increase reliability. Finally, at advanced process nodes, leakage is a critical issue, turning nearly all designs into advanced low-power designs.

A successful design flow must simultaneously consider power, performance, and area constraints in a seamless closed-loop, multi-objective planning-to-signoff solution. Power optimization techniques must combine seamlessly with advanced power switching and scaling techniques applied to power domains. But these advanced techniques can lead to component overhead and introduce new complexity to design, verification, and testability. To deliver successful low-power products on schedule, today’s design teams demand a holistic solution that manages complexity while reducing risk and increasing predictability.

Cadence Low-Power Solution: a complete design-to-signoff methodology
  • Comprehensive: Spans system realization (system modeling, architecture exploration, and validation of power management under software control); SoC realization (design planning, IP selection, and a library of highly power-efficient IP); and silicon realization (power-aware RTL-to-GDSII flow for digital and mixed-signal designs, and rigorous closed-loop dynamic and formal verification). Power intent is both pervasive and consistently interpreted throughout the flow.
  • Interoperable: Standards-based, supporting Si2’s Common Power Format (CPF) and power-aware verification methodologies leveraging the Accellera Universal Verification Methodology (UVM). Power format interoperability is supported with IEEE 1801 (UPF).
  • Proven: Introduced back in 2007 and has since amassed more than 500 successful advanced low-power tapeouts at many semiconductor companies around the globe.
  • Reduces risk: Closed-loop verification eliminates flaws, and power estimation increases predictability
  • Boosts productivity: Automates the latest low-power design techniques
  • Speeds time to market: Reduces iterations and eliminates re-spins
  • Increases quality: Easy power architecture analysis and advanced optimization engines help you meet power, performance, and area specs