Cadence Low-Power Methodology Kit
Streamlines the adoption of low-power techniques and optimizes their usage. Eliminates risk with a complete front-to-back methodology, best practices, checklists, and reference flows.
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Incisive Verification Kit
Automates and eases the adoption of reusable advanced verification techniques, increasing productivity and predictability. Teaches metric-driven verification methodology using interactive workshops and with integrated Incisive tool flows.
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Incisive Desktop Manager
Automates and guides the everyday deployment and visualization of verification tasks and results.
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Incisive Enterprise Manager
Automates and guides verification from planning to closure. Includes SystemVerilog and e functional coverage capabilities.
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Incisive Enterprise Simulator
Performs multi-language coverage-driven functional verification, analysis, and debug from system level to gate level. Automates testbench generation.
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Incisive Enterprise Specman Elite Testbench
Automates testbench generation and reuse to boost the productivity and quality of block, chip, and system verification.
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Incisive Formal Verifier
Performs formal analysis in the assertion-based verification and debug of RTL block designs, before testbench availability, to speed design convergence.
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Incisive Verification IP
Supports advanced testbenches, transaction-based acceleration for high-level testbenches, assertion-based VIP for formal, simulated, and accelerated block-level verification, and emulation and in-circuit verification. Available for a wide range of complex protocols (PCI Express, AMBA, USB, OCP, Ethernet, and more). OVM-compliant and supports a variety of IEEE-standard languages.
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Open Verification Methodology
Facilitates true SystemVerilog interoperability with a standard library and a proven methodology. Eases the development and usage of plug-and-play verification IP.
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