Globalization Demands Coherence
The coherent verification of hundreds of IP blocks operating in a single SoC requires a global team. That team can leverage local talent, but the physical distances can stress project coherence. Individual teams need to choose abstractions, standards, and use models that fit their skill sets, IP complexity, and role within the greater SoC verification project. No single engine, language, or methodology can pragmatically service this reality.
Only the Incisive platform fuses multiple engines, IEEE standard languages, verification domains, and methodologies to enable abstractions—from systems to silicon—for multiple use models that integrate coherently with a planning and management methodology.
Planning and Management at all Levels
Planning and management is the best path to project-level coherence. For example, the team that creates an executable plan and the associated randomized tests has a different set of quality/completion metrics from the team that creates Verilog RTL tests and instruments code coverage. If we consider all of the teams contributing to the SoC, the metrics include formal, analog, low-power, system-level, gate-level, and more. In this reality, there is no project-level coherence because there is no single set of metrics forming a comprehensive view.
Only Incisive Enterprise Manager provides the means to map these metrics to a hierarchical and executable plan, providing project managers with visibility across global SoC verification projects.
Systems to Silicon in Multiple Domains
Abstraction has addressed complexity since Moore stated his law nearly 50 years ago. Transistors, gates, RTL, and now SystemC are evidence of abstraction enabling design on increasingly greater scale. These digital abstraction layers are also evident in the analog and low-power domains. With each abstraction comes the specialization to verify specific aspects of the SoC aligned with the accuracy of that abstraction. The value of that specialization is lost when global teams repeat tasks best completed in other levels of abstraction.
Only Cadence provides the integration among the Virtuoso, Palladium, and Incisive platforms to enable continuous verification—from systems to silicon—across analog, digital, and low-power domains.
Task-Based Verification Focus
SoC, IP/subsystem, and gate-level handoff are the three verification tasks. Each one is defined by test style and length but diversify based on IP, skill set, and metrics. To verify mixed-signal, low-power, and systemic functionality, SoC tests typically run for hours to days across a mix of languages and abstractions. IP/subsystem verification requires up to tens of thousands of tests that verify specific functions. Gate-level verification is driven by functional, timing, and manufacturing tests that can run for a few weeks. Each task has unique performance, debug, language, and engine needs, but the lines between them blur as the SoC proceeds from definition, to development, integration, and on to silicon realization.
Only the Incisive environment provides the comprehensive support for standards, debug tools, engines, and methodology needed to smoothly move through these tasks to achieve complete SoC verification.
Unique Value
- Better productivity through high-speed engines, advanced debug techniques, and formal applications
- Greater predictability through the automation of verification planning and management
- Higher quality through highly accurate and comprehensive verification of digital and mixed-signal designs