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Synthesizable Ghz PHY 

Synthesizable DDR-SDRAM PHY is a third-generation, DFI-compliant PHY IP block which is a complete process-independent solution ready to be integrated into SoCs and ASICs which interface with DDR-SDRAM memories. Each configurable PHY is delivered to match the unique requirements of the customer's DDR application. Using the PHY reduces risk and time-to-market for deploying memory interfaces in silicon.

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Key Features:
  • Achieve a GHz PHY (DDR-3200 data rates), including synthesis, layout, and timing closure in four hours using a standard EDA toolset
  • Process node independent
  • Configurable for data width, ECC, low power, and many other options
  • Supports DDR4/3/2/1 and LP-DDR1/2 devices
Architecture
PHY design typically takes months with significant effort for timing closure, particularly at the high DDR memory interface speeds common today. The PHY solution includes timing closure and DFM, greatly reducing implementation time. The PHY is synthesizable and RTL-based which makes it much easier to take through back-end implementation. Synthesizable DDR PHY Architecture

Databahn DDRPHY Diagram

The RTL-based design provides flexibility to easily fit into your floorplan and allows you complete control of the padring. Other strengths, as compared to hard macros, include well known DFT and DFM techniques since the PHY is based on cells from your standard cell library. Because the PHY is built from standard cells, designers can use a normal, digital, automatic place-and-route flow.

Using the DDR PHY Interface (DFI) ensures re-usability since the same PHY may be used with different memory controllers. With DFI, all handling of multiple timing domains, data capture, and data re-synchronization happens within the PHY leaving memory controller logic as purely digital, with simple timing constraints.

PHY Features
  • Synthesizable GHz DDR PHY
    • Contains all DDR timing logic, single DLL or PLL per 8 bit slice
    • Complete DFI to I/O pad connections
    • Full place and route flow with basic layout and routing
  • Configurable and synthesizable
    • Configurable design to match application interface
    • Flexible I/O pad placement
    • Fully synthesizable (CTS-enabled)
    • Complete SDC and STA flow for optimized timing closure with standard place and route flows, providing full visibility
  • Extensive silicon-proven track record
  • Standard cell-based architecture, full place and route
  • DFI (DDR PHY Interface) compliance
  • Support for 8 or more ranks of memory, including DIMM support for large enterprise systems
  • Support for all foundry processes
  • Optional integrated analog DLL has fine delay step granularity (15ps or less)
  • Highly configurable (data width, ECC, I/O selection, I/O, and pad-ring placement)
  • Integrated I/O pads from multiple vendors
  • At-speed built-in loopback test
Design Features
Low-power consumption is important in all scenarios, not just mobile applications. Passive mode features include power control of the DDR pad bias current, selectable output drive level during quiet mode, and DLL power down capability, and datapath reduction mode.

The PHY data slice integrates several components including the DDR I/O pads and optionally, an analog DLL, to handle 8 bits of data. When using an analog DLL, the majority of the slice's area is dominated by the DLL. Multiple DDR PHY data slices are instantiated along with the address and control logic to assemble the PHY. Placement is flexible so that a PHY with arbitrary aspect ratio can be constructed.