Home > Solutions > Design IP > Memory > Cadence DDR Soft Phase PHY

Email
* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

Cadence Contacts

Global Office Locator
Find Offices worldwide »

Sales Inquiry
Request for Product information »
Cadence Channel Partners »

Corporate Headquarters
Cadence Design Systems, Inc.
2655 Seely Avenue
San Jose, CA 95134
Phone: 408.943.1234
* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Company Location *

Comments: *

Cadence DDR Soft Phase PHY 

Cadence DDR DRAM solutions are the only fully integrated IP offerings on the market with the features and configurability required to optimize your design and meet your performance, power, and cost targets. With more than 400 design wins ranging from the lowest-power handheld consumer applications to the highest-performance enterprise supercomputers, Cadence Design IP for DDR delivers a solution tailored to your design and is your lowest-risk path to success.

Cadence Design IP: DDR Phase PHY Technical Brief »

The Cadence DDR Phase PHY is designed for the highest-performance DDR3 and DDR4 devices, including low-voltage variants such as DDR3L and DDR3UL, at speeds up to DDR-3200. These memory classes may be freely intermixed to allow popular combinations such as DDR3/DDR4. Our DDR Phase PHY is ideal for applica¬tions such as enterprise, networking, computing, and digital TV.

The Cadence DDR Phase PHY is a hybrid analog/digital solution comprising a clock phase generation PLL and digital logic to perform all data capture and analysis based on the multiple phases of the clock. Our DDR Phase PHY connects the DDR I/O pads to the DFI interface to the memory controller including alignment of write data, read data capture, and DQS gating.

The architecture of the Cadence DDR Phase PHY is an over-sampling design that uses DSP-like techniques to reconstruct the data on the memory’s data lines, providing a robust output at the highest DDR DRAM speeds, even in the presence of noise. Our DDR Phase PHY offers an automated design flow with advanced synthesis and static timing analysis (STA) scripts that help you achieve RTL-to-placed gates in as little as four hours.



For total control over the DDR interface implementation, our Soft Phase PHY gives you complete flexibility with process, library, floorplan, I/O pitch, packaging, metal stack-up, routing, and other physical parameters.

Key Features
  • Supports up to DDR-2133 in 40nm
  • Current implementation supports up to DDR-2400 in 28nm
  • Future implementation supports up to DDR-3200 in 28nm and below
  • 8-bit datapath slice can be repeated to build PHYs of any width
  • Supports DRAM chips with 8 or 16 data bits per chip, commonly used in soldered-down and unbuffered DIMM (UDIMM/SoDIMM) applications
  • Supports DRAM chips with 4 data bits per chip, commonly used in registered DIMM (RDIMM) applications
  • Individual timing to each data slice supports DDR3 and DDR4 DIMM fly-by timing and unique board topologies
  • Read and write data interfaces employ phase-based delays for correct data and DQS alignment
  • PLL creates PVT-compensated read and write clocks to the appropriate data paths
  • Phase PHY design allows per-bit deskewing without any extra elements in the data path
  • Register interface for PHY programming, configuration, and testing modes
  • Clock gating for lowest power operation
  • Read and write leveling uses DFI PHY evaluation mode or controller evaluation mode
  • Scan functionality for data slice
  • Internal and external datapath loopback mode enables additional functional testing
  • Boundary scan muxing built into core logic facilitates insertion of boundary scan chains between core logic and I/O pads