Cadence NVM Express Interface Solution 

The NVM Express (NVMe) specification defines an optimized register interface, command set, and feature set for PCI Express (PCIe). The NVMe specification utilizes characteristics from PCIe to improve latency, performance, scalability and virtualization, and provides an efficient command set with a large capacity of queued and in-process commands. Cadence Design IP for NVMe Subsystem is a hardware end-to-end solution from PHY to SoC fabric, including a software stack that enables a complete subsystem solution. This delivers many advantages to the SoC design team by offering a complete verified subsystem block that terminates at a known point for hardware and a defined API interface for system software. The bus interconnects between PHY, PCIe controller, and NVMe are already optimized and require no additional logic.

Cadence NVM Express Interface Subsystem

Cadence Design IP: NVM Express Subsystem Technical Brief »

Cadence® Design IP for NVMe delivers a fully integrated solution that provides application-layer support for processing NVMe commands. The solution includes an NVMe Controller (which can be combined with the Cadence PCIe Controller and PHY), and an NVMe Subsystem—the industry’s first end-to-end hardware solution, from PHY to SoC fabric, including a software stack.

The Cadence NVMe Subsystem provides application-layer support for processing NVMe commands. Its autonomous queue management system fetches NVMe commands from the host memory. Individual or multiple data blocks are then transferred by direct memory access (DMA) within the NVMe Controller.

The software abstracts all NVMe Controller functionality for a local CPU with minimal application assistance, performing subsystem initialization and all commands that are not hardware-accelerated. To ease integration, the software uses a thin-specific layer behind a clean interface.

The Cadence NVMe Subsystem is also highly configurable, allowing many aspects to be customized according to your system requirements.

Features

NVMe Controller configuration options

• Configurable number of I/O queues up to the maximum of 65,536
• Size of I/O queue buffer is configurable
• Supports a maximum of between 100 and 2,000 outstanding commands at any one time
• Admin queue commands to create or delete I/O queues are handled autonomously without local firmware support
• Weighted round-robin with urgent arbitration mechanism
• Administrator command support
• Full support for memory-mapped NVMe registers

PCIe Controller configuration options

• Supports MSI and MSI-X PCI interrupt mechanisms; number of MSI-X interrupt vectors available (MSI-X table size) is configurable
• Supports bifurcation, SR-IOV, MIMO, and other PCIe features
• Supports up to 256 functions—physical (PF) or virtual (VF)—with ARI support
• Supports advanced SR-IOV features (flexible PF-VF mapping, configurable interrupt, and AER support per PF or VF)
• Fully configurable FIFOs and RAMs along with several options such as ECC, end-to-end datapath parity, and ECRC support
• Complies with PCI Express base 3.0 specification v1.0 and Intel PIPE 3.0 (v0.9)
• Configurable root complex, end point, or dual-mode support
• Supports X1 up to X16 lane configurations; X16 configuration performs dual-packet processing per cycle for maximum throughput
• Supports MSI, MSIx, and legacy interrupts and spec-required power management features

PCIe PHY configuration options

• Supports Gen1, Gen2, and Gen3 applications
• Multi-tap adaptive decision feedback equalization for long-reach support
• Automatic calibration of analog circuits and offset correction
• Analog dynamic feedback equalization (DFE) architecture for low power
• BIST functions for manufacturing test including loopback and pattern generator, error detector, and error counter
• Fully adaptive continuous-time linear equalizer
• On-chip regulation for high jitter performance

High performance, low power, lowest latency

The Cadence NVMe Subsystem allows you to achieve the lowest possible latency, from external interface to core fabric. You can develop optimized interfaces between the building blocks of the Subsystem, allowing the IP to reduce configuration options and thereby reduce the number of logic levels. This maximizes system performance while minimizing power.

Cadence NVM Express Interface Controller

The Cadence NVMe Controller provides application-layer support for processing NVMe commands. It is situated between a PCIe Controller and Flash Memory Controllers to provide the data transport required for SSDs.

Our NVMe Controller provides an autonomous queue management system to fetch NVMe commands from host memory without local firmware processing. Individual or multiple data blocks are then transferred by direct memory access (DMA) within the NVMe Controller when local firmware or additional hardware indicates the availability of Flash resources. The queue management system retains enough information about the NVMe command queues to reduce the overhead of continually accessing host memory other than for block data transfer.

Features such as the number of command queues supported, size of each queue, and maximum number of outstanding commands are all definable at RTL compile time. The design can be supplied with industry-standard system busses or with a FIFO interface to meet your specific needs.

Cadence Design IP: NVM Express Controller Technical Brief »

Key Features

• Supports NVM Express standard revision 1.0c
• Configurable number of I/O queues up to the maximum of 65,536
• Size of each I/O queue is configurable up to the maximum depth of 65,536 commands
• Supports a maximum of between 100 and 2,000 outstanding commands at any one time
• Admin queue commands to create or delete I/O queues are handled autonomously without local firmware support
• Low overhead block read/write
• Supports host memory page sizes from 4KByte to 128MByte
• Weighted round-robin with urgent arbitration mechanism
• Tiered data support
• Administrator command support
• Supports MSI and MSI-X PCI interrupt mechanisms; number of MSI-X interrupt vectors available (MSI-X table size) is configurable
• Full support for memory-mapped NVMe registers
• Supports bifurcation, SR-IOV, MIMO, and other PCIe features