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NAND Flash Controller IP
As storage moves away from traditional media, NAND Flash offers the mix of performance and cost required to support the latest applications. Controlling and interfacing with NAND Flash, however, poses a challenge when trying to maximize system-level performance. Cadence® Design IP for NAND Flash delivers the industry’s highest performance, most feature-rich, and most flexible NAND Flash solution that enables enterprise-class storage and embedded memory applications.
Cadence Design IP: NAND Flash Controller Technical Brief
»
Evaluate NAND Flash Controller IP
»
The Cadence NAND Flash Controller, combined with the Cadence
NAND Flash Soft PHY
, provides advanced capabilities for the latest NAND specifications. The Controller supports older legacy interfaces that are still widely used, and it provides unparalleled backward compatibility.
By hardware-accelerating many functions that are typically implemented in software, the Cadence NAND Flash Controller enables engineers to drastically improve performance while significantly reducing the integration effort.
Key Features
Universal Flash support across all vendors
BCH error correction optimized for different applications
Optional multi-level bit cell ECC ( 8, 16, 32, 64, and higher)
Auto-detect and auto-config to reduce boot loader code generation
Line-rate hardware detection and correction
ONFI 1,2,3 and Toggle 1,2 device support
Flash data width from 8 and 16 bits
Asynchronous or synchronous mode
Multiple low-power options
Support for SLC, MLC, and TLC boot operation
Data and command DMA available
Multi-plane operation
Read/write cache command support
Small data command support (partial page)
Volume and LUN addressing
Interlaced and NON-interlaced addressing
Silicon-proven, Scalable Design IP
The Cadence NAND Flash Controller has been widely deployed across a range of applications and devices―without silicon failures. Enabling so much hardware acceleration with so few issues demonstrates the robustness of the design in all silicon technol¬ogies, including FPGAs.
Superior Performance
The Cadence NAND Flash Controller has a performance-driven architecture that implements hardware acceleration for many functions typically done in firmware. Using the data and command DMA, the Controller can easily obtain within 10% of the theoretical maximum performance of the Flash device speci¬fication. For more random applications, the Controller supports partial page accesses.
Cadence Flash device support
Manufacturer
Device Type
Comments
Samsung
SLC/MLC
All known devices
Toshiba
SLC/MLC
All known devices, logical block addressing (LBA) supported
Hynix
SLC/MLC
All known devices
Micron
SLC/MLC
All known devices
ONFI 1
SLC/MLC
All known devices mode 1-5
ONFI 2.2, 3
SLC/MLC
All known devices mode 1-5
Toggle 1, 2
SLC/MLC
All known devices 166MHz
Cadence Design IP – DRAM Memory Controller Datasheet
Cadence Design IP – NAND Flash Memory Controller Datasheet
Cadence Design IP – PCI Express Gen 3 Controller Datasheet
EDA360: The Way Forward for Electronic Design
Content Query Web Part [2]
Cadence Design IP Evaluation
NAND Flash PHY IP
DDR PHY IP
DDR3 Webcast
Low Power DRAM White Paper
Toggle NAND Webcast
NAND White Paper
ONFi 2.1 Webcast