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Cadence Design IP: Wide I/O Controller 

Cadence Wide I/O DRAM solutions are the only fully integrated IP offerings on the market with the features and configurability required to optimize your design and meet your performance, power, and cost targets. With more than 400 design wins ranging from the lowest-power handheld consumer applications to the highest-performance enterprise supercomputers, Cadence Design IP for Wide I/O and DDR DRAM delivers a solution tailored to your design and is your lowest-risk path to success.

Cadence Design IP: Wide I/O Controller Technical Brief »

The memory subsystem is a core component of any SoC, and the DDR DRAM interface will have a fundamental impact on your system’s performance and power. Wide I/O is the latest-generation low-power DRAM standard, first published by JEDEC in January 2012. Ideal for low-power, wireless, and handheld applications, the Cadence Wide I/O Controller supports the latest Wide I/O DRAM standard.

Wide I/O takes an entirely new approach to power-efficient design. It uses a large number of through-silicon-via (TSV) connections between the SoC and the DRAM to allow a peak memory bandwidth of more than 100Gbits per second. Wide I/O is projected by manufacturers to use about half the power per bit of LPDDR2 technology. Cadence Design IP for Wide I/O takes our successful low-power DDR Controller design and ports all of its key features over to our Wide I/O Controller. In addition to supporting the latest Wide I/O features, existing features such as BIST have been expanded to match new properties of Wide I/O devices.

Cadence controllers include advanced low-power and security modules proven in some of the latest smartphone and tablet chipsets to deliver the lowest power possible while maximizing performance. A companion Cadence Design IP solution is available for DDR DRAM, supporting 10 different DRAM standards including low-power variants like LPDDR2 and LPDDR3.

Wide I/O Controller


Key Features
  • Supports Wide I/O DRAM memories compliant with JESD229
  • Supports typical 512-bit data interface from SoC to DRAM (4 x 128 bit channels) over TSV at 200MHz offering more than 100Gbit/sec of peak DRAM bandwidth
  • Independent controllers for each channel allow optimization of traffic and power on a per-channel basis
  • Supports 3D-IC chip stacking using direct chip-to-chip contact
  • Supports 2.5D chip stacking using silicon interposer to connect SoC to DRAM
  • Priority and quality-of-service (QoS) features
  • Flexible paging policy including autoprecharge-per-command
  • Two-stage reordering queue to optimize bandwidth and latency
  • Coherent bufferable write completion
  • Power-down and self-refresh
  • Advanced low-power module can reduce standby power by 10x
  • Supports single- and multi-port host busses (up to 32 busses with a mix of bus types)
  • Priority-per-command (AXI4 QoS)
  • BIST algorithm in hardware enables high-speed memory testing and has specific tests for Wide I/O devices