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Cadence DDR Phase PHY for TSMC 65LP, 40G, 28HP, and 28HPM 

Cadence® DDR DRAM solutions are the only fully integrated IP offerings on the market with the features and configurability required to optimize your design and meet your performance, power, and cost targets. With more than 400 design wins ranging from the lowest-power handheld consumer applications to the highest-performance enterprise supercomputers, Cadence Design IP for DDR DRAM is your lowest risk path to success.

Cadence DDR Phase PHYs are hard PHYs for TSMC 65LP, TSMC 40G, TSMC 28HP, and TSMC 28HPM processes, supporting high-performance DDR3 and DDR4 devices, including low-voltage variants such as DDR3L and DDR3UL, at speeds up to DDR-2400 in TSMC 28HP and TSMC 28HPM.

Cadence Design IP: DDR (Hard) Phase PHY for TSMC 65LP, 40G, 28HP, and 28HPM Processes Technical Brief»

The architecture of the Cadence DDR Phase PHY is an oversampling design that uses DSP-like techniques to reconstruct the data on the memory’s data lines, providing a robust output at the highest speeds of DDR DRAM, even in the presence of noise. With a slice-based architecture, our Hard PHY macros offer you flexibility in placement, floorplanning, packaging, and I/O while retaining the reliability and ease of use of Hard PHY designs. When delivered connected to I/Os, our Hard PHYs offer all the time-to-market advantages and proven design quality of traditional Hard PHY designs while retaining some flexibility.



The Cadence DDR Phase PHY is a hybrid analog/digital solution comprising a clock phase generation PLL and digital logic to perform all data capture and analysis based on the multiple phases of the clock. Our DDR Phase PHY connects the DDR I/O pads to the DDR PHY Interface (DFI) to the memory controller including alignment of write data, read data capture, and DQS gating.

Key Features
  • Up to 1200MHz (DDR-2400) operation in DDR4/3 mode in TSMC 28HP and TSMC 28HPM
  • Supports the highest speed of DDR3, up to 1066MHz (DDR-2133) operation in TSMC 40G
  • Supports the highest speed of DDR2, up to 533MHz (DDR-1066) operation in TSMC 65LP
  • Complete PHY available with I/Os connected
  • 8-bit datapath macros can be repeated to build PHYs of any width
  • Supports DRAM chips with 8 or 16 data bits per chip, commonly used in soldered-down and unbuffered DIMM (UDIMM/SoDIMM) applications
  • Supports DRAM chips with 4 data bits per chip, commonly used in RDIMM applications
  • Individual timing to each data slice supports DDR3 and DDR4 DIMM fly-by timing and unique board topologies
  • Read and write data interfaces employ phase-based delays for correct data and DQS alignment
  • PLL creates PVT-compensated read and write clocks to the appropriate data paths
  • Phase PHY design allows per-bit deskewing without any extra elements in the data path
  • Register interface for PHY programming, configuration, and testing modes
  • Clock gating for the lowest power operation
  • Read and write leveling using DFI PHY evaluation mode or controller evaluation mode
  • Scan functionality for data slice
  • Internal and external datapath loopback mode for additional functional testing
  • Boundary scan muxing built into core logic facilitates insertion of boundary scan chains between core logic and I/ O pads
  • I/O pads with termination calibration logic and data retention