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Cadence Design IP: DDR Controller 

Cadence DDR DRAM solutions are the only fully integrated IP offerings on the market with the features and configurability required to optimize your design and meet your performance, power, and cost targets. With more than 400 design wins ranging from the lowest-power handheld consumer applications to the highest-performance enterprise supercomputers, Cadence Design IP for DDR DRAM delivers a solution tailored to your design and is your lowest-risk path to success.

Cadence Design IP – DRAM Memory Controller Datasheet »

Evaluate DDR Memory Controller IP»

Cadence DDR Controller IP supports 10 different DRAM standards: DDR1, DDR2, DDR3, and DDR4; low-power DRAM (LPDDR1, LPDDR2, LPDDR3); and low-voltage DRAM (DDR2L, DDR3L, DDR3UL). These memory classes may be freely intermixed to allow popular combinations such as DDR4/DDR3/LPDDR2. A companion Cadence Design IP solution is available for Wide I/O–3D-IC designs using through-silicon vias.

Wide I/O Controller


In low-power, wireless, and handheld applications, the Cadence DDR Controller supports the latest mobile LPDDR DRAM standards. It includes advanced low-power and security modules proven in some of the latest smart¬phone and tablet chipsets to deliver the lowest power possible while maximizing performance.

In enterprise, networking, computing, and other high-performance applications, the Cadence DDR Controller supports the latest high-speed DDR3 and DDR4 devices— either on-board or on DIMM—and it supports advanced error correction and data protection required by these applications.

In consumer and cost-sensitive applications, the perfor¬mance of Cadence DDR Controller IP maximizes the bandwidth of lower-cost DRAM devices to reduce the overall product bill of materials.

Key Features
  • Supports all major memory standards; a Wide I/O Controller is also available
  • Supports RDIMM including SSTE32882 and parity
  • Supports UDIMM including SoDIMM
  • Industry-standard DFI PHY interface
  • Priority and quality-of-service features
  • Flexible paging policy including autoprecharge-per-command
  • Two-stage reordering queue to optimize bandwidth and latency
  • Coherent bufferable write completion
  • Error correction coding (ECC) allows SEC/DED over 32 or 64 bits on busses of 16, 32, 64, or 128 bits
  • Power-down and self-refresh
  • Boot-time programmable DRAM width reduction enables operation on full or half data width while keeping the same memory map
  • Supports single- and multi-port host busses (up to 32 busses with a mix of bus types)
  • Priority-per-command (AXI4 QoS)
  • Advanced low-power module can reduce standby power more than 10x and active power by 50%