DDR Memory Controller IP 

Cadence Design IP for DDR is the industry-leading IP solution for high-performance DDR memory controllers. It reduces risk and speeds time-to-market for deploying memory interfaces in silicon. The DDR memory controller IP is currently licensed for use in over 260 designs and is implemented in over 100 chips in silicon. DDR IP provides chip designers with the ability to configure the optimal memory controller IP for performance, power and gate-count requirements.

Robust configurability and state-of-the-art features to effectively insulate SoC designers from fast-changing protocols and details associated with DRAM device technology. Cadence DDR IP's advanced multi-port arbitration engine ensures optimal data transfer to all SoC clients. DDR memory controller cores are also highly configurable and designed to work optimally for consumer, enterprise and mobile applications. DDR memory controller IP is vendor/process independent and provides configurable support for DDR1, DDR2, DDR3, DDR4, Wide-IO, LPDDR1, LPDDR2 and LPDDR2-NVM devices. DDR IP can be efficiently configured for design-specific requirements, and are also available as pre-configured cores optimized for key market applications.

Cadence Design IP: Wide-I/O Controller Technical Brief»

Evaluate DDR Memory Controller IP»

Key Features:

• Extreme performance, high bandwidth, and low-latency from an advanced reordering engine
• Configurable to fit unique design characteristics
• Silicon-proven with 260+ design wins & 100+ chips in silicon
• Supports popular on-chip bus standards incl. AXI4, AXI, AHB, and OCP

Architecture

• Advanced and configurable architecture allows maximum performance in a wide range of different system environments
• Popular SoC interface bus standards such as AXI4, AXI, AHB and OCP are supported. Traffic can come from a single requestor or may be arbitrated from multiple ports using a choice of different flexible arbitration algorithms in the arbitration engine
• A command queue holds a list of upcoming commands and the ordering engine reorders commands for user-assigned priority and increased bandwidth while maintaining coherency
• The transaction processing unit watches the command queue and does memory preparation for future commands in advance, so that commands may execute as soon as they reach the head of the queue
• Performance and power tuning registers use parameters from Cadence SOMA files as input to get the maximum performance from each memory; performance and power can be further enhanced with a range of adjustments
• Uses the DFI interface to the PHY, allowing the use of Cadence's PHY, a range of available 3rd party PHYs, or the customer's own PHY
• Supports all the major DRAM devices: DDR1, DDR2, DDR3, DDR4, Wide-IO, LPDDR1, LPDDR2, and LPDDR2-NVM

Features

• Supports DDR1, DDR2, DDR3, DDR4, Wide-IO
• LPDDR1, LPDDR2 & LPDDR2-NVM from all DRAM vendors
• Compliant to the DDR PHY Interface spec. (DFI)
• Choose from several, DFI-compliant physical interface options
• Optimized for device specific features & functionality
• Fully pipelined design with flow control for commands & data
• Configurable for performance, power, & area requirements
• Multi-port system interface with configurable arbitration
• Programmable priority algorithms
• Built-in sequencing & ordering engines
• Optional functionality/modules for ECC & BIST
• Special low-power modes for reducing memory power, increasing battery life or reducing cooling needs
• Comprehensive verification environment, leveraging Cadence verification IP and memory models
• Vendor & process independent IP
• Complete deliverables for integration verification, & silicon deployment

Cadence Design PHY Interface

The DFI-compliant PHY is a complete solution ready to be integrated into SoCs and ASICs which interface with DDR memories. Each PHY is delivered to match the unique requirements of the customer's DDR application. Using Cadence's PHY reduces risk and time-to-market for deploying memory interfaces in silicon. More PHY details regarding features and deliverables is now available. Cadence Design IP also supports DFI compliant PHYs from third-party IP providers and ASIC vendors. For more info about DFI, visit: www.ddr-phy.org.

Performance Operations

• Command look-ahead, to prepare pages in memory in advance of when commands execute
• Bank splitting to reorder transactions destined for different rows in the same bank, page grouping to reorder transactions destined for the same page in memory, and read-write reordering to sequence reads and writes to avoid bus turn-arounds

The overall intent of the DDR Design IP performance operations is to give class-leading performance from all traffic types – even if the traffic is not known at design time. The low-power option provides a central point for control of power in the external memory, automatically selecting the power mode of the external memory based on the traffic that is passing through the controller.

Foundry Process

Cadence Design IP for DDR is silicon proven with more than 260 design wins and 100 designs in silicon spanning all process nodes. Here are proven supported process technologies. If you have any questions regarding support for a particular process node, please contact Cadence sales.

Markets

The DDR memory controller IP is used in a wide range of markets and applications. DDR Design IP can be efficiently configured for design-specific requirements, and are also available as pre-configured cores optimized for key market application.

Customers

"Denali's PCIe core and PureSpec verification IP are integral enablers in meeting the PCIe Gen 2.0 specifications. Today's demanding data center networks address their increasing traffic needs by incorporating our latest accelerated 1Gb and 10Gb Ethernet products. Denali's reputation and track record speaks volumes for creating and delivering high-quality, complete IP solutions for the latest process technologies."

Rafy Carmon
VP of R&D
Percello, Ltd.

"During the design of our new WiFi SoC (CL1300), we prioritized performance and time to market. Denali's unmatched reputation for a high-performance, configurable DDR controller IP provided an optimal solution for the DDR DRAM subsystem and has allowed us to meet the requirements for carrier-grade video streaming."

Lior Weiss
VP of Marketing
Celeno Communications

Partners

Carbon Design Systems provides cycle-accurate models for all SDRAM memory interface IP in the Databahn portfolio, including support for the latest DDR3, DDR2, and LPDDR2 specifications. Carbon provides solutions which enable automatic generation of TLM models, architectural analysis, system performance validation and pre-silicon hardware/software integration. carbondesignsystems.com