PCIe is the industry leading IP solution which reduces risk and speeds time-to-market for deploying PCI Express (PCIe) interfaces in silicon. The PCIe controller IP conforms to the latest PCI-SIG specifications and has been validated against the leading PCIe verification tools and tested in silicon with commercial motherboards and adapter cards.
The PCIe controller IP provides chip designers with the ability to configure the optimal PCIe controller IP for power, performance, and gate-count requirements. Pre-configured the PCIe controller cores are also available to provide customers with off-the-shelf IP pre-designed specifically for consumer,
enterprise, and mobile applications.
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PCI Express Gen3 Controller Datasheet »
PCI Express Gen 1/2 Controller
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PCI Express M-PCIe Controller Datasheet »
Local Management InterfaceThe core provides a 32-bit management interface through which
local software can read and write registers in the core. Software can access registers in the configuration space as well as
local management registers (registers containing the configuration settings of the core, debug registers, status registers, etc.).
Host Application Layer InterfaceFive distinct simple interfaces for master, memory, I/O,
messaging, and interrupt transactions hide PCIe complexity. The memory Read/Write interface is for access to memory controllers or
DMA. The master Read/Write interface is to initiate requests from the Endpoint as a bus master. The I/O interface support PCIe I/O
transactions. The messaging interface supports customer messaging across PCIe and the interrupt interface supports all interrupts
from the user application to the PCIe core.
Each instance of the core can be configured as an Endpoint (EP) or Root Complex (RC).
Power managementThe core supports PCIe link power states L0, L0s and L1 with only the main power. With auxiliary power, it can support L2 and L3 states. The core supports the new L1 sub-states with CLKREQ ECN to provide additional low power modes of operation.
Interrupt supportThe core supports all the three options for implementing interrupts in a PCIe device: Legacy, MSI and MSIx modes. In the Legacy mode, it communicates the assertion and de-assertion of interrupt conditions on the link using Assert and De-assert messages. In the MSI mode, the core signals interrupts by sending MSI messages upon the occurrence of interrupt conditions. In this mode, the core supports up to 32 interrupt vectors per function, with per-vector masking. Finally, in the MSI-X mode, the controller supports up to 2048 distinct interrupt vectors per function with per-vector masking.
Credit ManagementThe core performs all the link-layer credit management functions defined in the PCIe specifications. All credit parameters are configurable.
Configurable Flow-Control UpdatesThe core allows flow control updates from its receive side to be scheduled in a flexible manner, thus enabling the user to make tradeoffs between credit update frequency and its bandwidth
overhead. Configurable registers control the scheduling of flow-control update DLLPs.
Replay BufferThe Controller IP incorporates fully configurable link-layer reply buffers for each link designed for low latency and area. The core can maintain replay state for a configurable number of outstanding packets.
Host InterfaceThe datapath on the host interface is configurable to be 32, 64, 128 or 256-bits. It may be AXI or Host Application Layer (HAL) interface. An optional DMA controller is also available.
"Denali's PCIe core and PureSpec verification IP are integral enablers in meeting the PCIe Gen 2.0 specifications. Today's demanding data center networks address their increasing traffic needs by incorporating our latest accelerated 1Gb and 10Gb Ethernet products. Denali's reputation and track record speaks volumes for creating and delivering high-quality, complete IP solutions for the latest process technologies."
VP of Engineering
"To scale network performance to 10Gbps and beyond, the NFP-3240 offers a fully compliant PCIe v2.0 implementation including SR-IOV with 256 queues for network I/O co-processing in heterogeneous IA/x86 designs. When faced with the important decision as to which IP vendor has the most reputable and silicon-proven PCI Express IP, Denali Software was the preferred vendor that met our critical high throughput and feature requirements. We rely on Denali's high-quality, interoperable design and verification IP solutions and excellent customer support to meet the PCIe 2.0 and IOV specifications, our product development timeframes, and achieve a competitive advantage."
Sr. Vice President of Silicon Engineering
"Current chipsets demand higher-bandwidth support and chip-to-chip interconnectivity and Denali's IP products support the next-generation protocol requirements for design and verification of PCI Express systems. Denali's IP products help us streamline our design cycles and provide a clean roadmap for incorporating the latest specifications for our deployment of PCI Express technology."
Logic Design Manager
Engenio Storage Group