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Cadence PCI Express Hard PHY 

The Cadence PCIe PHY for the TSMC 28nm High-Performance Mobile (HPM) process is a Hard PHY macro supporting PCIe Gen3, Gen2, and Gen1 speeds. The Hard PHY is part of a complete solution for PCI Express that also includes a controller, verification IP, and design-in kits.

PCI Express Gen3 PHY Datasheet »

Our PCIe Hard PHY consists of a physical media attachment (PMA) layer and a soft physical coding sub-layer (PCS). The PCS complies with PIPE 3.0 v0.9 specifications and provides support for the dynamic equalization features of PCIe Gen3. Cadence design-in kits provide flexibility in board design.

Key Features
  • Supports Gen1, Gen2, and Gen3 applications
  • Supports X1, X2, X4, X8, and X16 configurations
  • Supports a low input reference clock frequency of 100 MHz
  • PCS compliant to PIPE3.0 v0.9
  • Multi-tap adaptive decision feedback equalization for long-reach support
  • Fully adaptive continuous-time linear equalizer
  • On-chip regulation for high jitter performance
  • Analog Dynamic Feed Back Equalization (DFE) architecture for low power
  • Automatic calibration of analog circuits and offset correction
  • Clock data recovery with racking range to support multiple reference clocking schemes
  • Programmable multi-tap transmitter finite-impulse-response filter with polarity inversion
  • On-demand eye/bathtub curve measurement capability
  • BIST functions for manufacturing test including loopback and pattern generator, error detector, and error counter
  • Analog test bus for test and characterization
  • Three levels of interfaces for flexibility and ease of use
    • Primary mode interface
    • Advanced mode interface