will be under system maintenance from Tuesday June 28, 6pm PT to Sunday July 3, 11pm PT. Login and registration will be disabled.
Home > Solutions > Advanced Node Solution > Technologies

Advanced Node Solution 

Manufacturability signoff
Cadence manufacturability signoff solutions offer technologies for litho- and CMP-aware design, silicon diagnostics, and mask data preparation. These technologies prevent manufacturing effects from disrupting electrical performance, they analyze systematic and random variability on designs, and they optimize designs to maximize yield.

Digital design flows for advanced process nodes require a comprehensive RTL-to-GDSII solution. Encounter® Digital Implementation (EDI) System delivers a complete solution for variation- and manufacturing-aware design closure, low power, mixed-signal implementation, and integrated signoff in a single, scalable multi-CPU–enabled design environment for high-capacity, high-performance digital implementation.

In addition, to help users create manufacturing-robust designs, Virtuoso® Analog Design Environment gives designers access to a new parasitic estimation and comparison flow and optimization algorithms. These algorithms help to center designs better for yield improvement and advanced matching and sensitivity analyses.

With its innovative graph-based architecture and superthreading technology, Cadence NanoRoute® Router provides the speed and capacity required to design large chips. Its SMART2 technology holistically addresses timing, area, power, and manufacturability constraints during physical implementation of complex SoCs.

Timing analysis
From front-end logic design through back-end digital implementation, Encounter Timing System provides a unified timing engine with advanced capabilities for signal integrity, thermal, and statistical static timing analyses.

Power analysis
Encounter Power System provides consistent, converging power analysis and power rail integrity analysis across the design and implementation flow—spanning floor/power planning, physical implementation, optimization, and signoff.

Parasitic extraction and analysis
Fast and accurate parasitic extraction and analysis is the key to timing closure and high quality of silicon. Cadence QRC Extraction supports advanced capabilities for all nanometer-scale design styles, including RF, analog, mixed signal, custom digital, and cell.

The production-proven Virtuoso Spectre® Circuit Simulator is the industry-leading analog SPICE circuit simulator with comprehensive foundry support. It now includes new "turbo" technology, boosting performance by 5–10x while ensuring silicon accuracy, to help designers verify their designs efficiently.

Null Response.