At advanced process technology nodes, even the slightest perturbations in the design flow can cause dramatic swings in design integrity. Design teams face a predictability crisis riddled with silicon failures, performance degradation, and prolonged design schedules. Smaller transistors and wires pose a challenge to manufacturability. Escalating data volume and denser, more complex chips are testing the limits of traditional routing architectures. And new process and design innovations, such as high-k metal gate, SOI, and 3D-packaging, are intensifying the pressures of adoption and rapid deployment.
To tackle these obstacles, engineers need a design environment and methodology that considers all advanced node design requirements simultaneously in a seamlessly integrated multi-objective planning-to-signoff solution.
An integrated solution for digital and full-custom implementation
The Cadence® Advanced Node Solution provides a complete, consistent, and converging flow across Encounter® digital and Virtuoso® custom implementation technologies to address design-for-manufacturing (DFM) and variability effects (lithography, CMP, thermal, and process variations) in the early stages of the design flow. By integrating model-based DFM and statistical technology in a comprehensive prevention-analysis-repair flow, the Cadence solution is capable of handling huge designs and provides significant productivity gains over traditional DFM-closure solutions.
To tackle advanced DFM issues and improve yield, the Cadence Advanced Node Solution includes a patented interconnect optimization technology with unique a 3D shape- and space-based approach to model, analyze, and optimize true shapes and intervening physical spaces. It allows shapes and spaces to be positioned in the exact configuration and location required to correct sub-wavelength manufacturing effects. This capability affords the best combination of precision and flexibility when optimizing interconnects using tiered foundry and recommended design and manufacturing constraints—leading to the highest yield and best quality of silicon.
The Cadence Advanced Node Solution:
- Reduces risk: By integrating comprehensive DFM analysis into the flow, design teams can prevent downstream problems and eliminate re-spins.
- Boosts productivity: By preventing the majority of DFM issues upfront and by leveraging unique proprietary algorithms for single and multi-CPU speed-up, design teams can increase their productivity.
- Speeds ramp to volume: By reducing the number of iterations within the flow and limiting silicon re-spins, design teams can achieve fast, predictable time to market and high volume production.
- Increases yield: Using the integrated DFM and unique 3D shape technology, design teams can optimize interconnect to achieve the highest yield and quality of silicon.