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Home > Solutions > Advanced Node Solution

 Advanced Node Solution 

  • Overview
  • Digital
  • Custom / Analog
Innovative capabilities for custom/analog designs at advanced nodes It's well documented that designing at advanced-process nodes is extremely complicated and painfully expensive. With this in mind, system-on-chip (SoC) solutions must have the right mix of features, functionality, and performance to justify designing at these nodes. But of most concern to custom/analog designers are the challenges that arise from the complexity of manufacturing. The Cadence® Virtuoso® advanced-node platform has an innovative set of capabilities that enables designers to take full advantage of the silicon at these process nodes.

Density gradient effect avoidance

Designing at 20nm, 16nm, 10nm Advanced Process Nodes What makes designing at 20nm/16nm/14nm/10nm/7nm advanced nodes unique is the deep, complex interdependency of manufacturing and variability, on top of increasing power and performance specifications.

These concerns include the following:
  • Multiple-patterning technology (MPT) and color-aware physical design, including double, triple, quadruple, and penta-patterning
  • Layout-dependent effects (LDE) and density-gradient effects (DGE), in which the layout context—what is placed near to a device—can impact device performance by as much as 30%
  • Sophisticated color-aware custom routing
  • Exponentially increasing physical design rules
  • Device variation and sensitivity
  • New transistors types (e.g., FinFETs)
EM violation avoidance

Virtuoso Advanced Node Platform The Virtuoso advanced-node platform improves individual point tools to handle these challenges, as well as enables new design methodologies that allow for rapid layout prototyping, in-design signoff, and close collaboration between schematic and layout designers—essential to designing efficiently at advanced-process nodes.

The latest release of the Virtuoso advanced-node platform includes:
  • Robust support for FinFET-based designs, requiring MPT to manage device variability and sensitivity on the circuit design
  • Many enhanced interactive and automated capabilities to support a structured layout methodology with features such as core editing commands, interactive wire editor, module generators (ModGens), fully automated custom routing, and assisted placement, all design rules checking (DRC) and coloring correct
  • Unique and close integration with the Virtuoso physical verification system (PVS), enabling signoff verification support for both DRC and coloring decomposition within the Virtuoso Layout Suite
Multiple-patterning support and color-aware physical design

  • Increases quality of silicon: Custom design platform re-engineered from the ground up to support the most aggressive advanced-node processes to take full advantage of process technology.
  • Boosts designer productivity: New design methodologies along with the introduction of targeted automation techniques greatly enhance productivity of both circuit designers and layout engineers. Leveraging these flows and technologies can increase designer productivity by up to 5X versus traditional design tools and flows.
  • Accurately predict and manage variability: Close collaboration with leading foundries provides capabilities within the Virtuoso Advanced-Node platform that enables designers to predict and manage variability up front in the design flow, thereby avoiding costly design respins due to process variability.
  • Industry leader in advanced-node custom design: The Virtuoso Advanced-Node platform supports and is certified by all major advanced 20/16/14/10/7nm technologies.

in-design design rule checking
Digital Faster design convergence at 28nm and 20nm requires fully integrated and comprehensive DFM capabilities. It also requires more complex timing models to handle larger designs. Encounter® Digital Implementation (EDI) System’s advanced node design technology prevents and corrects harmful lithography hotspots, random defects, on-chip variation, and variation due to chemical-mechanical polishing. Using rule- and model-based in-design analysis (pre-qualified and closely correlated with foundry process simulation), EDI System guides design implementation, minimizes risk upfront, and prevents unexpected design re-spins and late-stage iterations.

The latest release of EDI System introduces 20nm design implementation and signoff capabilities with correct-by-construction double-patterning support. These double-patterning capabilities span floorplanning, placement, optimization, routing, parasitic extraction, and signoff for timing, power, and physical verification of 20nm designs. This correct-by-construction approach to advanced node design ensures faster turnaround time in meeting performance, power, and reliability targets while yielding high-quality results in silicon.
  • Placement engine optimizes cell placement for double-patterning requirements, leading to better area efficiency
  • NanoRoute® Advanced Digital Router with FlexColor technology routes in a correct-by-construction manner; metal is routed to be DRC- and double-patterning–correct using a built-in physical verification engine during all stages of routing
  • Cadence QRC Extraction produces multi-value SPEF files required for litho-biasing support and mask-misalignment modeling
  • Encounter Timing System utilizes min. and max. capacitance values on early and late launch and capture clock paths for setup and hold timing analysis
  • Encounter Power System utilizes multi-valued SPEF parasitics for power, IR drop, and AC/DC EM analyses
  • Encounter Timing System considers intrinsic waveform effects during signoff timing analysis, including back-miller current effect that acts as an aggressor to affect timing delay
  • Cadence Physical Verification System provides in-design signoff for DRC and double-patterning conflict checks
Advanced Node: The Natural Progression Toward Achieving Performance, Power, and Area Differentiation in Your End Products Advanced process nodes promise tremendous advantages in power, performance, and design capacity—but they also introduce some tough design challenges, such as increased timing and power variability, more complex layout rules, and incredibly large designs with massive amounts of IP.

A major new challenge at 20nm/14nm is the requirement for extra masks (double patterning technology, or DPT) to make existing lithography work at this advanced node. Read 20 questions on 20nm - a Q&A document. Escalating data volume and denser, more complex chips are testing the limits of traditional routing architectures. Even the slightest perturbations in the design flow can cause dramatic swings in design integrity. Engineers face a predictability crisis riddled with silicon failures, performance degradation, and prolonged design schedules. And new process and design innovations—high-k metal gate, SOI, 3D-IC packaging—are intensifying the pressures of adoption and rapid deployment.

To manage lower power, higher performance goals in smaller form factors, engineers need a design environment and methodology that considers all advanced node design and manufacturing requirements simultaneously. This requires a seamlessly integrated, multi-objective planning-to-signoff solution.

Cadence Advanced Node Solution: Comprehensive and Proven Design-to-Signoff Solution for Design and Manufacturing Closure The Cadence® Advanced Node Solution provides a complete, consistent, and converging flow across Encounter® digital and Virtuoso® custom implementation technologies to address design-for-manufacturing (DFM) and variability effects (lithography, CMP, thermal, process variations) in the early stages of the design flow. By integrating color-aware DPT flows with model-based DFM, IR drop analysis, timing and power analysis, and verification in a comprehensive prevent-validate-finalize flow, the Cadence solution can tackle huge designs and provides significant productivity gains over traditional design closure methodologies.

  • Increases quality of silicon: Multi-CPU–enabled, advanced, and integrated DPT-aware engines for digital and custom implementation, analysis, and verification.
  • Boosts productivity: Automated handling of large, low-power, mixed-signal designs with context-aware placement and routing, in-design signoff, and verification prevents the majority of verification and DFM issues upfront.
  • Speeds ramp to volume: Reduces the number of iterations within the flow and limits silicon re-spins.
  • Manages yield: Variation-aware in-design signoff and integrated DFM flows allow you to optimize interconnect.