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Advanced Node Solution
Press Releases
Cadence Low-Power, Advanced-Node Digital Technology Incorporated Into SMIC 40nm Reference Flow
UMC Adopts Cadence 40-Nanometer Reference Flow for Low Power, Verification, Implementation and DFM-Aware Design
Cadence Achieves First-Silicon Results on 32nm Common Platform™ Technology
Freescale Achieves Design Cycle Reduction and Superior Silicon Predictability with Cadence Model-Based Physical and Electrical DFM Solutions
Cadence Validates ARM Optimized Libraries for 45nm SOI Process
Cadence Announces that STMicroelectronics Adopts Encounter Signoff Solutions for Designs from 65 to 32 Nanometers
Articles
Heard at DAC: the Question on Everyone’s Mind
EDA360: My Modest Opinion
On-Chip Thermal Analysis Is Becoming Mandatory
Addressing manufacturing variation at advanced nodes with silicon-contour-based DFM
SPIE and the IC design world: a wall starts coming down
Signoff for Manufacturability
Cadence DFM - WYDIWYG; Interview with Mike McAweeney
Process Intelligent Modeling and Statistical STA improve DFM
Cadence fills out DFM flow in time for 45-nm design
Challenges at the 45-nm node are great
Content Query Web Part [1]
Cadence Delivers 28-Nanometer Design Capabilities to TSMC Reference Flow 10.0
Modeling Stress-Induced Variability Optimizes IC Timing Performance White Paper
Recent Blog Posts
“In Design” DFM Signoff – the Inside Story
Rapid Analog Prototyping - Handcrafted Layout Gets a Needed Productivity Boost
28 nm IC Design: The Devil Is In The Details
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