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SKILL Language Programming v6.1.2

SKILL Language Programming v6.1.2 Delivery Method: Instructor-Led Item ID: ES_SG_83018_6.1.2 Length: 5 Days Category SKILL Item De

Date: 5 Sep 2010
http://www.cadence.com/training/sg/pages/coursedetails.aspx?componentid=es_sg_83018_6.1.2&componenttypeid=crse&revisiondate=1276055700000

Incisive Verification IP Family for DDR2/3

Date: 2 Sep 2010
http://www.cadence.com/products/fv/Pages/ddr.aspx

Cadence Announces Development of OVM Verification IP for USB 3.0 and PCI Express 3.0 High-Speed Protocols

SAN JOSE, Calif., 17 Nov 2008 Cadence Announces Development of OVM Verification IP for USB 3.0 and PCI Express 3.0 High-Speed Protocols

http://www.cadence.com/cadence/newsroom/press_releases/pages/pr.aspx?xml=111708_usb

Virtuoso Connectivity-Driven Layout vIC 6.1.3.500.5

Virtuoso Connectivity-Driven Layout vIC 6.1.3 Delivery Method: VIRTUAL Item ID: ES_84462VC_IC 6.1.3.500.5 Length: 16.00 Hours (4 sessions) List P

Date: 5 Sep 2010
http://www.cadence.com/training/na/pages/coursedetails.aspx?componentid=es_84462vc_ic 6.1.3.500.5&componenttypeid=crse&revisiondate=1253305680000

Low Power #3: Low Power Flow, Physical Implementation and Formal Verification v1.0

Low Power #3: Low Power Flow, Physical Implementation and Formal Verification v1.0 Course ID:ES_82197_1.0 Duration:3 Days. Course Description In this course, you explore the low-power flow in imp

http://www.cadence.com/training/eu/Pages/coursedetails.aspx?courseid=es_82197_1.0

Specman Elite Basics for Verification Environment Developers v8.1

Specman Elite Basics for Verification Environment Developers v8.1 Delivery Method: Instructor-Led Item ID: ES_SG_82138_8.1 Length: 3 Days Cat

Date: 5 Sep 2010
http://www.cadence.com/training/sg/pages/coursedetails.aspx?componentid=es_sg_82138_8.1&componenttypeid=crse&revisiondate=1269270300000

Allegro Package Designer v16.2

Allegro Package Designer v16.2 Delivery Method: Instructor-Led Item ID: ES_SG_85022_16.2 Length: 4 Days Category Back End Item Desc

Date: 5 Sep 2010
http://www.cadence.com/training/sg/pages/coursedetails.aspx?componentid=es_sg_85022_16.2&componenttypeid=crse&revisiondate=1269272580000

Cadence Introduces the EDA Industry’s First Verification Solution for PCI Express 3.0

SAN JOSE, Calif., 01 Oct 2009 Cadence Introduces the EDA Industry’s First Verification Solution for PCI Express 3.0

http://www.cadence.com/cadence/newsroom/press_releases/pages/pr.aspx?xml=093009_pci

Digital Physical Implementation #3: Power Analysis and Signal Integrity Checking v1.0

Digital Physical Implementation #3: Power Analysis and Signal Integrity Checking v1.0 Course ID:ES_82173_1.0 Duration:1 Day. Course Description This Design Foundations course combines theory and

http://www.cadence.com/training/eu/Pages/coursedetails.aspx?courseid=es_82173_1.0

Cadence Advances Segmentation Strategy with 3 Tiers of Verification Products and Methodologies

SAN JOSE, Calif., 24 Oct 2005 Cadence Advances Segmentation Strategy with 3 Tiers of Verification Products and Methodologies

http://www.cadence.com/cadence/newsroom/press_releases/pages/pr.aspx?xml=102405_segmentation