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Sigrity OrbitIO 

Assign I/Os and place devices in a full system context

Rapid system prototyping and early assessment of pad ring-to-board‒level connectivity, for single- and multi-die package configurations, within a single environment.

Cadence Sigrity OrbitIO Datasheet »
Product ImageSigrity OrbitIO technology helps system design teams assess pad ring‒to‒board-level connectivity in a single environment. This enables I/O assignment and device placement decisions to be made in a full system context. OrbitIO is easily deployed in Cadence® or Synopsys IC design flows and offers support for Cadence and other popular package/board design tools.

Unlike iterative and spreadsheet-based approaches, OrbitIO allows you to make and refine decisions using the best available data - with a single tool - thus reducing errors, complexity, and cost.

  • Plans chip-package-board designs in a unified co-design environment
  • Prototypes pad ring and package for early feasibility assessment
  • Validates wirebond feasibility during early design planning
  • Plans multi-die I/O for SiP, PoP, TSV, and stacked-die packages
  • Determines flip-chip bump pattern and route feasibility
  • Optimizes pad-ring layout for multiple package variants
  • Supports both top-down and bottom-up approaches to system design
  • Reduces cost and complexity by minimizing over-design
  • Anticipates and avoids downstream issues with early design planning
  • Visualizes the full interconnect hierarchy, from pad-ring level to PCB, in a single tool
  • Expedites planning by utilizing best-available or virtual design data
  • Easily incorporates new design content and processes incremental updates
  • Quickly generates design abstractions in response to marketing requests
  • Avoids the costs and limitations of proprietary or scripted solutions