Sigrity 2016 Sigrity 2015 ASI 16.64 ASI 16.63
DesignCon 2016: Sigrity 2016 Portfolio Highlights
Ken Willis, Cadence product engineering director, discusses the company's DesignCon 2016 highlights ranging from serial link analysis and DDR/LPDDR support to the Sigrity 2016 portfolio's new products and enhancements including generating AMI models and a quasi-static field solver.
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Sigrity 2016 Portfolio Improves Product Creation Time with PCB Design and Analysis Methodology for Multi-Gigabit Interfaces
Cadence expanded its Sigrity™ technology portfolio with new products and capabilities:
- Upgraded serial link analysis flow
- Optimized design flows
- Upgraded 3D interconnect modeling
- Upgraded serial link analysis flow to accelerate the time to pass compliance tests
- New IBIS-AMI model building technology takes industry-proven equalization algorithms and provides a wizard-based graphical interface to rapidly facilitate creation of IBIS-AMI models. Available in two tiers, one that enables creation of models strictly for Sigrity tools, and another that creates models suitable for any IBIS-AMI compliant simulator.
- New cut-and-stitch model extraction technology allows for segmenting long serial links into sections that should be modeled using 3D full-wave and sections that can be modeled using hybrid extraction technology. The resultant model is extracted 10X faster than a strictly 3D full-wave extraction with 95% accuracy.
- New USB 3.1 (Gen 2) compliance kit to confirm that the 10Gbps interface requirements are met.
- Optimized design flow between PCB designer and power integrity engineer
- New cross-probing between DC analysis report file and Allegro® editing canvas
- Batch DC analysis available directly from the Allegro editing canvas
- Review previously generated DC analysis report files from the Allegro editing canvas
- Optimized design flow between IC package designer and characterization engineer
- Batch electrical performance assessment (EPA) available directly from the IC package designer’s editing canvas
- Batch package model creation using hybrid solver technology directly from the IC package designer’s editing canvas
- Review previously generated EPA report data from the IC package designer’s editing canvas
- Upgraded 3D interconnect modeling to enable rapid modeling of low-cost PCB and IC packages
- New rapid and accurate capacitance extraction technology
- Quickly produce RLCG interconnect models for designs with few (or no) power and ground planes/shapes using new 3D quasi-static extraction technology
DesignCon 2015: Sigrity 2015 Portfolio Highlights
Brad Brim, Cadence product engineering architect, discusses the company's DesignCon 2015 highlights ranging from power-aware design for parallel buses and serial interconnect design to the Sigrity 2015 portfolio new products and enhancements including support for LPDDR4.
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Cadence Expands Sigrity 2015 Technology Portfolio with New Products, LPDDR4 Compliance Checks, and Flexible Licensing Options
The expanded Cadence® Sigrity™ technology portfolio offers:
- Sigrity Parallel Computing 4-pack
- Sigrity System Explorer, an updated power-aware system signal integrity (SI) feature
- Flexible purchasing options for PCB and IC package design and analysis
Sigrity Parallel Computing 4-Pack
Sigrity Parallel Computing 4-pack is a license that allows designers to run parallel computing tasks across four additional computers, thereby accelerating product creation time and tripling the speed of PCB extraction of signoff-accurate interconnect models.
Sigrity System Explorer
Sigrity System Explorer features general-purpose topology exploration, enabling power-aware signal integrity and transient power integrity (PI) analysis across multiple fabrics. It can be used for what-if analysis of signals, power, or both signals and power together. The software enables signal and power integrity analysis using interconnect models that are pre-route (what-if), captured from measurement, or extracted using electromagnetic field (EM) tools such as Cadence Sigrity PowerSI® or Sigrity PowerSI 3D EM Full-Wave Extraction tools.
Power-Aware System Signal Integrity Support for LPDDR4
The power-aware system signal integrity (SI) feature now supports LPDDR4 analysis with full JEDEC
compliance checking, including bit-error rate analysis with high capacity channel simulation for memory interface.
Product Bundle Options
Cadence product bundles provide flexible licensing options for small analysis teams with big analysis requirements. These bundles include:
- Combined license for Allegro® Sigrity SI and Allegro Sigrity PI base products, when a single user is responsible for both SI and PI tasks.
- Combined System SI license for both Serial Link and Parallel Bus analysis, when a single user is responsible for both memory interfaces and SerDes interfaces.
SystemSI – Parallel Bus
When simulating a DDR4 interface in Sigrity™ SystemSI™, we now have added the ability to validate JEDEC’s DDR4 bit error rate (BER) requirement of 1e-12. This is accomplished by running high-capacity channel simulation on the DDR4 data bus.
System SI – Testbench
A new general version of Sigrity SystemSI is available to simulate single-ended or differential signals traveling on either single or multiple fabrics. The Sigrity SystemSI testbench can be used as a power-aware topology simulation tool (using IBIS models) that connects interconnect models that are either pre-route or extracted.
Allegro- Sigrity PI base
DRC Markers – IR drop analysis will now create DRC markers. These DRC markers can be loaded into the Allegro® environment to pinpoint the areas that need to be corrected.
Reduced setup time when iterating – When a design is edited and renamed after analysis has been performed, the same setup information can be reused from the previous analysis despite the new .brd file name.
Support for the Latest High-Speed Interfaces
DDR4 Power-Aware Signal Integrity Analysis now includes DQ eye masks.
USB 3.0 Compliance Checks now available in Serial Link Analysis solution.
EMA Timing Designer Integration for Complete DDR3/DDR4 Timing Closure
Graphical timing spreadsheets show full interface timing relationships.
TimingDesigner and Allegro® Sigrity™ Power Aware Signal Integrity—the industry’s most complete timing analysis and timing reporting solution.
SI and PI Base Integration with XtractIM
Automatic recognition of package type, component recognition, die bump, and package solder profile, etc.
Batch mode: XtractIM workspace file (.ximx) is automatically generated and RLCG and SPICE model will be generated automatically.
GUI mode: The workflow setup is automatically completed when launching XtractIM, and model extraction and electrical performance assessment are just a mouse click away.
Allegro Sigrity Integration improvements
Common waveform and report formats.
Accelerated time-to-analysis as Allegro to Sigrity data conversion is now accomplished through direct read/write.
Allegro constraint generation from Sigrity SystemSI.