SystemSI – Parallel Bus
When simulating a DDR4 interface in Sigrity™ SystemSI™, we now have added the ability to validate JEDEC’s DDR4 bit error rate (BER) requirement of 1e-12. This is accomplished by running high-capacity channel simulation on the DDR4 data bus.
System SI – Testbench
A new general version of Sigrity SystemSI is available to simulate single-ended or differential signals traveling on either single or multiple fabrics. The Sigrity SystemSI testbench can be used as a power-aware topology simulation tool (using IBIS models) that connects interconnect models that are either pre-route or extracted.
Allegro- Sigrity PI base
DRC Markers – IR drop analysis will now create DRC markers. These DRC markers can be loaded into the Allegro® environment to pinpoint the areas that need to be corrected.
Reduced setup time when iterating – When a design is edited and renamed after analysis has been performed, the same setup information can be reused from the previous analysis despite the new .brd file name.
Support for the Latest High-Speed Interfaces
DDR4 Power-Aware Signal Integrity Analysis now includes DQ eye masks.
USB 3.0 Compliance Checks now available in Serial Link Analysis solution.
EMA Timing Designer Integration for Complete DDR3/DDR4 Timing Closure
Graphical timing spreadsheets show full interface timing relationships.
TimingDesigner and Allegro® Sigrity™ Power Aware Signal Integrity—the industry’s most complete timing analysis and timing reporting solution.
SI and PI Base Integration with XtractIM
Automatic recognition of package type, component recognition, die bump, and package solder profile, etc.
Batch mode: XtractIM workspace file (.ximx) is automatically generated and RLCG and SPICE model will be generated automatically.
GUI mode: The workflow setup is automatically completed when launching XtractIM, and model extraction and electrical performance assessment are just a mouse click away.
Allegro Sigrity Integration improvements
Common waveform and report formats.
Accelerated time-to-analysis as Allegro to Sigrity data conversion is now accomplished through direct read/write.
Allegro constraint generation from Sigrity SystemSI.