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Home > Tools > Sigrity Technologies > Allegro Sigrity SI/PI Solution

 Cadence SI / PI Analysis - Sigrity 

  • Allegro Sigrity SI Solution
  • Allegro Sigrity PI Solution
  • Cadence IO-SSO Solution
  • Cadence PDN Solution
 
Cadence Power Delivery Network Solution
Chip/Package/Board Co-Analysis
With the emphasis on low power and high performance, today’s electronics systems have vast amounts of technology packed into compact spaces. To operate efficiently, the systems need a continuous supply of power over a long period of time without any break, while remaining at an acceptable temperature.

When designing chips for these systems, power analysis has traditionally focused strictly on analyzing electromigration (EM) and IR drop of the chip. However, since all power delivered to a chip begins as a voltage source and travels through at least a PCB and IC package before the power arrives at the chip, a number of assumptions are made when the PCB and IC package are ignored. With smaller geometries and even lower power, the inaccuracies associated with ignoring IC package effects can make the difference between first-time success and having to re-spin the chip design.


Power integrity analysis from chip to package to board


Cadence is now bringing together power integrity solutions for chip, IC package, and PCB to enable a co-analysis solution that brings greater accuracy and lets design teams predictably determine power integrity across chip, package, and board. The ground-breaking Voltus™ IC Power Analysis Solution has been interfaced with Sigrity™ IC package and PCB power analysis technology to provide a complete system co-analysis solution.

Chip-Centric Co-Analysis Solutions
IR drop analysis and thermal analysis are important signoff tasks for chip designers. The Voltus™ IC Power Analysis Solution reads models generated by Sigrity™ packaging technology to provide a higher degree of accuracy than what can be determined with chip-level data alone. These chip-centric co-analysis techniques helps ensure first-time success:
  • Chip/package connectivity through model connection protocol (MCP) data
  • Better prediction of IR drop with included package model data
  • Thermal co-analysis through iterative power map and thermal map data exchange between chip and package analysis engines




With tight power margins, accuracy is a key requirement for IR drop analysis of semiconductors. The Voltus solution provides fast and accurate results on its own. With added information regarding the package parasitics, it will provide even greater accuracy. Sigrity XtractIM™ technology produces package models that are easy to connect to the Voltus solution. Together, the Voltus and Sigrity technologies provide an IR drop and thermal analysis solution that will produce signoff-accurate results for chip designers.

System-Centric Co-Analysis Solutions
Because proper power integrity analysis requires a team effort, chip designers and package designers must work together closely. When die information is shared with the package analysis team, power integrity problems can be pinpointed and fixed before it is too late. Cadence® Sigrity™ power integrity tools read Voltus™ die model data to ensure that chip, package, and PCB can all be included when evaluating the performance of the power delivery network (PDN):
  • System-centric DC analysis
  • System-centric AC analysis
  • System-centric IO-SSO analysis




With low power becoming a high priority for electronic designs, power integrity can no longer be an afterthought. A system-centric power integrity co-analysis flow keeps PDN design as a forethought throughout the design process. The Voltus IC Power Analysis Solution and Sigrity technology operate successfully on individual fabrics and ensure that the full system is represented to provide signoff-level accuracy for both power integrity and power-aware signal integrity.

With DC, AC, and simultaneous switching output (SSO) concerns simulated with signoff-level accuracy across chip, package, and PCB, you can build your design with confidence knowing that efficient, sufficient, and stable power will be delivered to your semiconductors under all operating conditions.
Products
Chip-Centric Co-analysis Solution System-Centric Co-analysis Solution
Cadence IO-SSO Solution The system engineer responsible for IO-SSO and the effects it has on the DDR memory system will be happy to know that all the technology needed for successful simulation is now available in a single suite of analysis tools, Cadence® IO-SSO Analysis Suite.


Cadence IO-SSO Analysis Flow


Design Flow While the system designer is responsible for looking at the various topologies and analyzing the effects of simultaneous switching outputs, there are a number of interconnect models required to perform effective simulations. In addition, the simulations will be much faster if performed with power-aware SI models over transistor-level SPICE models. The IO-SSO Analysis Suite allows the designer to start with native design files for the I/O, chip, package, and PCB, and either convert or extract those models into a format that can be dropped into the SystemSI topology editor.



Once the models are in the system topology editor, the system designer goes through a process of connecting the models together. This includes the connections for signal, power, and ground. When the models are extracted using XcitePI, XtractIM, and PowerSI, model connection protocol (MCP) headers will appear in each model making the connectivity much more intuitive.



With the models connected in the topology editor, DDR simulation results can be acquired. With power-aware IBIS models and interconnect models with coupled signal, power, and ground, the simulation will include noise-causing ground bounce and power drop. With simultaneous switching outputs, noisy power and ground rails will actually change the waveforms of the signals. Only with this accurate simulation of signal, power, and ground can accurate prediction of simultaneous switching noise be accomplished.



With accurate waveform capture, SystemSI will carefully analyze the data and report back the compliance with DDR4 and other popular memory interfaces. The report data is nicely captured in HTML format, and includes compliance criteria for waveform quality, eye quality, timing, and delay.



The IO-SSO Analysis Suite from Cadence provides an accurate and complete solution from a single EDA vendor. Given the design data for the chip, package, and PCB, a user of the IO-SSO Analysis Suite can extract all the fabrics into broadband interconnect models where signal, power, and ground are all coupled. In addition, transistor-level SPICE models can be converted to power-aware IBIS models. With the IO and interconnect models, DDR simulations can be run where the effects of simultaneous switching outputs are considered in the compliance criteria. Analysis data can be trusted as signoff quality as all the effects from non-ideal power and ground have been considered.
Products
Cadence IO-SSO Analysis Suite
Related Information
Allegro Sigrity PI Solution Our power integrity tools, integrating Cadence® Allegro® and Sigrity™ technologies, provide signoff-level, accurate PI analysis for PCBs and IC packages.
  • Unique full-featured base + options solution
  • Integral piece of the front-to-back constraint-driven PCB/package design flow
  • Integrated thermal and DC analysis nicely integrated to the design environment
Allegro Sigrity PI Solution Datasheet »


Allegro Sigrity PI Base
The Allegro Sigrity PI Base provides first-order DC analysis and guidance on decoupling capacitor placement. Power-Integrity constraint sets pass design intent from the component selection process to design implementation, reducing design iterations.
Learn more »
Allegro Sigrity PI Signoff and Optimization Option
The Allegro Sigrity Power Integrity Optimization and Signoff Option to the Allegro Sigrity PI Base provides a complete power integrity solution across packages and boards. The solution includes thermal-aware DC analysis, AC analysis, and decoupling capacitor optimization.
Learn more »
Allegro Sigrity Package Assessment and Extraction Option
Comprised of industry-leading Sigrity technologies, this option enables signal and PDN performance assessment, 2D and 3D analysis, electrical model extraction, and signoff report generation for IC Packages. This option can also be used with the Allegro Sigrity SI Base.
Learn more »
Products
Allegro Sigrity PI Base + Options
Related Information
Allegro Sigrity SI Solution Our power-aware SI tools, integrating Cadence® Allegro® and Sigrity™ technologies, provide signoff-level, accurate SI analysis for PCBs and IC packages.
  • A unique full-featured Base + Options solution
  • Integral piece of the front-to-back constraint-driven PCB/package design flow
  • Power-aware SI of high-speed memory interfaces is nicely integrated with the design environment

    Allegro Sigrity SI Solution Datasheet »

Allegro Sigrity SI Base
The Allegro Sigrity SI Base provides advanced interconnect modeling and SI simulation in support of constraint development and electrical analysis of high-speed designs. It simulates high-speed signals at the package, board, or multi-board level
Learn more »
Allegro Sigrity Power-Aware SI Option
The Allegro Sigrity Power-Aware SI Option to the Allegro Sigrity SI Base provides a complete solution for the analysis of source synchronous parallel buses, such as DDR3 and DDR4. Comprised of industry-leading Sigrity technologies, this option enables extraction of combined signal and power delivery networks.
Learn more »
Allegro Sigrity Serial Link Analysis Option
The Allegro Sigrity Serial Link Analysis Option to the Allegro Sigrity SI Base provides a complete solution for the analysis of multi-gigabit serial links.
Learn more »
Allegro Sigrity Package Assessment and Extraction Option
Comprised of industry-leading Sigrity technologies, this option enables signal and PDN performance assessment, 2D and 3D analysis, electrical model extraction, and signoff report generation for IC Packages. This option can also be used with the Allegro Sigrity SI Base.
Learn more »
Products
Allegro Sigrity SI Base + Options
Related Information