Cadence Power Delivery Network SolutionChip/Package/Board Co-Analysis
With the emphasis on low power and high performance, today’s electronics systems have vast amounts of technology packed into compact spaces. To operate efficiently, the systems need a continuous supply of power over a long period of time without any break, while remaining at an acceptable temperature.
When designing chips for these systems, power analysis has traditionally focused strictly on analyzing electromigration (EM) and IR drop of the chip. However, since all power delivered to a chip begins as a voltage source and travels through at least a PCB and IC package before the power arrives at the chip, a number of assumptions are made when the PCB and IC package are ignored. With smaller geometries and even lower power, the inaccuracies associated with ignoring IC package effects can make the difference between first-time success and having to re-spin the chip design.
Power integrity analysis from chip to package to board
Cadence is now bringing together power integrity solutions for chip, IC package, and PCB to enable a co-analysis solution that brings greater accuracy and lets design teams predictably determine power integrity across chip, package, and board. The ground-breaking Voltus™ IC Power Analysis Solution has been interfaced with Sigrity™ IC package and PCB power analysis technology to provide a complete system co-analysis solution. Chip-Centric Co-Analysis Solutions
IR drop analysis and thermal analysis are important signoff tasks for chip designers. The Voltus™ IC Power Analysis Solution reads models generated by Sigrity™ packaging technology to provide a higher degree of accuracy than what can be determined with chip-level data alone. These chip-centric co-analysis techniques helps ensure first-time success:
- Chip/package connectivity through model connection protocol (MCP) data
- Better prediction of IR drop with included package model data
- Thermal co-analysis through iterative power map and thermal map data exchange between chip and package analysis engines
With tight power margins, accuracy is a key requirement for IR drop analysis of semiconductors. The Voltus solution provides fast and accurate results on its own. With added information regarding the package parasitics, it will provide even greater accuracy. Sigrity XtractIM™ technology produces package models that are easy to connect to the Voltus solution. Together, the Voltus and Sigrity technologies provide an IR drop and thermal analysis solution that will produce signoff-accurate results for chip designers. System-Centric Co-Analysis Solutions
Because proper power integrity analysis requires a team effort, chip designers and package designers must work together closely. When die information is shared with the package analysis team, power integrity problems can be pinpointed and fixed before it is too late. Cadence® Sigrity™ power integrity tools read Voltus™ die model data to ensure that chip, package, and PCB can all be included when evaluating the performance of the power delivery network (PDN):
- System-centric DC analysis
- System-centric AC analysis
- System-centric IO-SSO analysis
With low power becoming a high priority for electronic designs, power integrity can no longer be an afterthought. A system-centric power integrity co-analysis flow keeps PDN design as a forethought throughout the design process. The Voltus IC Power Analysis Solution and Sigrity technology operate successfully on individual fabrics and ensure that the full system is represented to provide signoff-level accuracy for both power integrity and power-aware signal integrity.
With DC, AC, and simultaneous switching output (SSO) concerns simulated with signoff-level accuracy across chip, package, and PCB, you can build your design with confidence knowing that efficient, sufficient, and stable power will be delivered to your semiconductors under all operating conditions.