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 Cadence SI / PI Analysis - Sigrity 

  • Allegro Sigrity SI Solution
  • Allegro Sigrity PI Solution
  • Cadence IO-SSO Solution
 
Cadence IO-SSO Solution The system engineer responsible for IO-SSO and the effects it has on the DDR memory system will be happy to know that all the technology needed for successful simulation is now available in a single suite of analysis tools, Cadence® IO-SSO Analysis Suite.


Cadence IO-SSO Analysis Flow


Design Flow While the system designer is responsible for looking at the various topologies and analyzing the effects of simultaneous switching outputs, there are a number of interconnect models required to perform effective simulations. In addition, the simulations will be much faster if performed with power-aware SI models over transistor-level SPICE models. The IO-SSO Analysis Suite allows the designer to start with native design files for the I/O, chip, package, and PCB, and either convert or extract those models into a format that can be dropped into the SystemSI topology editor.



Once the models are in the system topology editor, the system designer goes through a process of connecting the models together. This includes the connections for signal, power, and ground. When the models are extracted using XcitePI, XtractIM, and PowerSI, model connection protocol (MCP) headers will appear in each model making the connectivity much more intuitive.



With the models connected in the topology editor, DDR simulation results can be acquired. With power-aware IBIS models and interconnect models with coupled signal, power, and ground, the simulation will include noise-causing ground bounce and power droop. With simultaneous switching outputs, noisy power and ground rails will actually change the waveforms of the signals. Only with this accurate simulation of signal, power, and ground can accurate prediction of simultaneous switching noise be accomplished.



With accurate waveform capture, SystemSI will carefully analyze the data and report back the compliance with DDR3, LPDDR3, and other popular memory interfaces. The report data is nicely captured in HTML format, and includes compliance criteria for waveform quality, eye quality, timing, and delay.



The IO-SSO Analysis Suite from Cadence provides an accurate and complete solution from a single EDA vendor. Given the design data for the chip, package, and PCB, a user of the IO-SSO Analysis Suite can extract all the fabrics into broadband interconnect models where signal, power, and ground are all coupled. In addition, transistor-level SPICE models can be converted to power-aware IBIS models. With the IO and interconnect models, DDR simulations can be run where the effects of simultaneous switching outputs are considered in the compliance criteria. Analysis data can be trusted as signoff quality as all the effects from non-ideal power and ground have been considered.
Products
Cadence IO-SSO Analysis Suite
Related Information
Sigrity PI Solution Cadence® PI tools, based on Sigrity™ technology, provide signoff-level accuracy for AC and DC power analysis of PCBs and IC packages.
  • Sigrity PI tools are offered as a solution suite
  • Signoff-accurate PI
  • Complete power delivery system analysis across chips, packages, and boards
AC Power Simulation
Advanced signal integrity, power integrity, and design-stage EMI solutions help designers guarantee results. Sigrity tools support S-parameter model extraction and provide robust frequency domain simulation for entire IC package and PCB designs.
DC Power Simulation
Sigrity tools help designers achieve efficient DC signoff for IC package and PCB designs, with electrical/thermal co-simulation to maximize accuracy. With these tools you can quickly pinpoint IR drop and current hotspots, and automatically find best remote sense locations.
Decoupling Capacitor Optimization
Sigrity technology enables design teams to balance decoupling capacitor (decap) cost and performance for PCBs and IC packages. Decap cost savings of 15% to 50% are typical. These tools support pre and post-layout decap studies, identify impedance issues, and suggests placement locations for EMI decaps.


Sigrity PowerSI
An advanced signal integrity, power integrity, and design-stage EMI solution. Supports S-parameter model extraction and provides robust frequency domain simulation for entire IC package and PCB designs.
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Sigrity PowerDC
An efficient DC signoff solution for IC package and PCB designs, with electrical/thermal co-simulation to maximize accuracy. Quickly pinpoints IR drop and current hotspots. Automatically finds best remote sense locations.
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Sigrity OptimizePI
A highly automated board and IC package AC frequency analysis solution. Supports pre-and post-layout decap studies, identifies impedance issues, and suggests placement locations for EMI decaps. Decap implementations are optimized for performance and cost.
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Sigrity PowerSI 3D EM Full-Wave Extraction Option
Full-wave solver for IC package and PCB capable of accurate analysis of complex 3D structures
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Products
Sigrity PI Suite
Related Information
Sigrity SI Solution Our power-aware SI tools, integrating Cadence® Allegro® and Sigrity™ technologies, provide signoff-level, accurate SI analysis for PCBs and IC packages.
  • A unique full-featured Base + Options solution
  • Integral piece of the front-to-back constraint-driven PCB/package design flow
  • Power-aware SI of high-speed memory interfaces is nicely integrated with the design environment

    Allegro Sigrity SI Datasheet »

Allegro Sigrity SI Base
The Allegro Sigrity SI Base provides advanced interconnect modeling and SI simulation in support of constraint development and electrical analysis of high-speed designs. It simulates high-speed signals at the package, board, or multi-board level
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Allegro Sigrity Power-Aware SI Option
The Allegro Sigrity Power-Aware SI Option to the Allegro Sigrity SI Base provides a complete solution for the analysis of source synchronous parallel buses, such as DDR3 and DDR4. Comprised of industry-leading Sigrity technologies, this option enables extraction of combined signal and power delivery networks.
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Allegro Sigrity Serial Link Analysis Option
The Allegro Sigrity Serial Link Analysis Option to the Allegro Sigrity SI Base provides a complete solution for the analysis of multi-gigabit serial links.
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Allegro Sigrity Package Assessment and Extraction Option
Comprised of industry-leading Sigrity technologies, this option enables signal and PDN performance assessment, 2D and 3D analysis, electrical model extraction, and sign-off report generation for IC Packages.
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Products
Allegro Sigrity SI Base + Options
Related Information