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Allegro Sigrity Serial Link Analysis Option 

Multi-Gigabit SerDes channel compliance

The Allegro® Sigrity™ Serial Link Analysis Option to the Allegro Sigrity SI Base provides a complete solution for the analysis of multi-gigabit serial links. Comprised of industry-leading Sigrity technologies, this option enables bit error rate (BER) prediction of complex serial links, including modeling of adaptive SerDes equalization in IBIS-AMI format.

Allegro Sigrity SI Datasheet »

The Allegro Sigrity Serial Link Analysis Option is comprised of a number of Sigrity tools that enable a serial link analysis solution that begins with model creation, moves to simulation, and winds up with automated comparison of simulation report data against compliance specifications.

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Allegro Sigrity Serial Link Analysis Option provides a comprehensive environment for design and accurate assessment of high-speed serial links.

The following Sigrity technology will be included with the Allegro Sigrity Serial Link Analysis Option to enable a complete solution for the analysis of multi-gigabit serial links:
  • Transistor-level model translator converts SPICE models to behavioral I/O models, removing the need for third-party SPICE simulators during multi-gigabit simulation
  • A power-aware hybrid solver extraction engine, enabling S-parameter extraction of complete coupled signal topologies together with their power distribution network (PDN)
  • A full-wave 3D solver for high-frequency interconnect extraction of detailed structures within IC packages and PCBs
  • A model utility that enables S-parameter viewing, checking, tuning, and conversion to Broadband SPICE macromodel format
  • A block-level schematic environment to model complex chip-package-board(s) serial link channels, including model connection protocol (MCP) to link each block, with high-capacity channel simulation, IBIS-AMI model support, and BER analysis
  • Electrical compliance checking of simulation results against today’s most popular multi-gigabit standards
Design Flow
Serial link analysis can begin at the earliest stages of design, before schematic netlists and physical layouts are available. Feasibility studies can be performed with full die-to-die channel topologies for the serial link of interest using a transmission line editor, a via creation tool, and sample AMI models.

As the design progresses, pre-layout models can be replaced with more detailed extracted models in a top-down methodology. When IBIS buffer models are not available, transistor-level models can be converted to IBIS and used to represent the I/O circuit models for the transmitter and receiver, coupled with AMI models for equalization. Interconnect modeling using accurate field solver engines can be used to create detailed post-layout S-parameter extraction of physical layout, and populate blocks in the schematic simulation environment. These S-parameters can be converted to SPICE subcircuits if desired, to accelerate simulation time and enhance convergence. Finally, detailed verification and compliance checking can be performed to determine final margins, BER, and compliance with industry-standard protocols.

  • Easy-to-use block-level schematic simulation environment
  • High-capacity channel simulation
  • Hybrid solver for efficient S-parameter extraction of large interconnect structures
  • 3D full-wave solver for detailed extraction of high-frequency structures
  • S-parameter tuning, checking, and Broadband SPICE model convers
  • Electrical compliance checking against multi-gigabit standard specifications
The Allegro Sigrity Serial Link Analysis Option together with the Allegro Sigrity SI Base enables a single user access to the following Sigrity products in either point tool mode or as an integrated Allegro Sigrity solution: