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Allegro Sigrity SI 


Advanced signal quality analysis

Provides advanced interconnect modeling and signal integrity simulation in support of constraint development and electrical analysis of high-speed designs. Simulates high-speed signals at the package, board, or multi-board level.

Allegro Sigrity SI Datasheet »
Integrated with Cadence® Allegro® PCB and IC Package design, editing, and routing technologies, Allegro Sigrity™ SI provides advanced signal integrity (SI) analysis both pre- and post-layout. Operating early in the design cycle allows for “what if” scenario exploration, sets more accurate design constraints, and reduces design iterations.

Allegro Sigrity SI reads and writes directly to the Allegro PCB and IC Package design database for fast and accurate integration of results. It provides a SPICE-based simulator and embedded field solvers for extraction of 2D and 3D structures. It supports transistor-level and behavioral I/O modeling, including power-aware IBIS 5.0 model generation. Parallel bus and serial channel architecture can be explored pre-layout to compare alternatives, or post-layout for a comprehensive analysis of all associated signals.

Features/Benefits
  • Performs a wide variety of SI analyses, including power-aware SI
  • Early detection of design errors to increase first-pass success
  • Sets accurate constraints, quickly and early in the process
  • Improves product performance through solution-space exploration
  • Explores alternative topologies in the earliest stages
  • Supports modeling and testing for multi-gigahertz signals
  • Generates S-parameters from signal topologies or analyzes signals in S-parameter format
  • Generates estimated crosstalk tables to increase design efficiency
  • Performs post-layout verifications directly from Allegro PCB and IC Package design canvas
  • Enables device, bus, board, package, and system model creation, modification, and verification
  • Verifies multiple-board and silicon-package-board signal paths