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Protium Rapid Prototyping Platform 

Enhanced productivity and ease-of-use in FPGA-based prototyping

The Cadence® Protium™ rapid prototyping platform is our second-generation advanced FPGA prototyping platform for early, pre-silicon software development, throughput regressions, and high-performance system validation. Expanding the Cadence System Development Suite, the Protium platform improves software development productivity, supports higher capacity, and facilitates faster bring-up compared to its predecessor and to other FPGA-based prototyping solutions.

“The ability to use the same bring-up flow for Palladium emulation and Protium rapid prototyping, allows our design teams to switch seamlessly between the two execution engines, which reduces the prototype bring-up time from months to weeks compared to traditional FPGA-based prototyping approaches. Additionally we expect to improve overall development productivity by extending the use of Protium rapid prototyping platform to the area of hardware/software co-verification.”
Hideya Sato, Deputy Executive General Manager, Global MONOZUKURI Division, Information & Telecommunication Systems Company, Hitachi, LTD

While FPGA-based prototyping is widely used today, with current prototyping tools, it can be both challenging and time-consuming to implement your design into an FPGA-based prototype. This is partly because you need to make some changes to the register-transfer level (RTL) design and also because there hasn’t been an easy transition available from an existing simulation or emulation environment to the prototype. The Protium platform, based on Xilinx Virtex-7 2000T FPGAs and featuring an advanced implementation and debug software flow, addresses these challenges.

The Protium platform is the next generation of Cadence’s popular Rapid Prototyping Platform (RPP). Both platforms are compatible with the Cadence Palladium® XP verification computing platform and Cadence SpeedBridge® Adapters, facilitating a fast and smooth transition of an existing emulation environment into a high-performance rapid prototype.

Compared to competitive solutions, the Protium platform reduces prototype bring-up time by up to 70%, shortening the process from months to weeks. The platform supports up to 100 million gates, which is a 4X increase in capacity compared to the first-generation Rapid Prototyping Platform. With a fully automatic software flow, the Protium platform delivers high performance that can be further optimized with user-driven optimizations, essential for early software development. Other Protium features include:
  • Automated memory compilation
  • External bulk memory support
  • RTL name preservation throughout the flow, which minimizes manual FPGA bring-up steps and debug to speed up time to market
  • Unique, easy-to-use debug capabilities, including signal monitoring, force/release signal, internal memory upload/download, probes, and cross FPGA triggering
Key Protium Platform Benefits
  • Fast compilation and partitioning: up to 75 million gates/hour, with virtually no design size limitation
  • Automatic, emulation-like clock tree transformation, supporting unlimited number of user clocks, gated-clock, latch, and internal tri-states
  • Single-ended and high-performance LVDS pin multiplexing
  • Fully integrated FPGA place-and-route tool, with automatic generation of all constraints and switches
Main Steps in the Protium Flow
Step 1: Import and compile/synthesize the design. The Protium platform uses the Palladium integrated compile engine, which ensures compatibility with simulation and emulation and enables reuse of existing scripts, constraints, clock definitions, memory definitions, and much more. The output here is a netlist that’s optimized for FPGAs with ASIC memories already converted and mapped into FPGA memories.

Step 2: Partition the design into multiple FPGAs. Here, the Protium platform will also convert gate clocks and latches into FPGA-friendly structures, address internal tri-states, add pin multiplexing between the FPGAs, and connect external interfaces, like PCI Express®, Ethernet, and more. This step generates one individual netlist per FPGA for subsequent place and route, as well as a verification model for validating design functionality before the time-consuming place-and-route step. Since debug and potential iterations to achieve prototyping functionality and performance goals are done before the place-and-route step, you can perform multiple iterations a day.

Step 3: FPGA place and route to generate individual bit files for the FPGAs. Set-up for the place-and-route tool is handled automatically, which frees you from dealing with place-and-route constraints, switches, and time-consuming experimentation to get good results.


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