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Cadence Palladium XP Series 


The Cadence® Palladium® XP series offers unmatched capabilities for simulation, acceleration, and emulation, making it the industry’s most advanced verification computing platform. Using the platform, you can achieve early hardware/software co-verification and benefit from flexible support for hard/soft intellectual property (IP) modeling.

Building on the strengths of the widely adopted Palladium XP platform, the latest generation Palladium XP II platform extends the capacity envelope to 2.3 billion gates while delivering up to 50 percent performance improvement for system-on-chip (SoC) verification. It increases verification throughput via faster upload speeds and improved debug, while preserving best-in-class simulation acceleration and emulation capabilities in a single platform. With the new platform, you can achieve faster post-silicon bring-up.
Palladium XP II Technical Brief  |   Palladium XP Technical Brief
Palladium XP Demos (Preview) | Palladium XP Demos (Full Version)
In-Circuit Acceleration Demo (Preview) | In-Circuit Acceleration Demo (Full Version)
UVM-Acceleration, Assertions and Coverage Demo (Preview)
UVM-Acceleration, Assertions and Coverage Demo (Full Version)
Industry’s First Verification Computing Platform – Palladium XP Series
With the Palladium XP series, you can gain a level of design and verification performance and scalability not previously available. See how NVIDIA and Zenverge stay ahead of the game with the Palladium XP Series. Hear Gary Smith on the system-level verification industry and Cadence's continued market-leading position. And watch how the Palladium XP platform accelerates Nethra Imaging's system-level verification. View the videos »

121 resources found
 
Title Type Rated
Protium Rapid Prototyping Platform Datasheet
Format: .PDF    Date: 17 Jul 2014
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Cynthesizer Solution
Format: .PDF    Date: 21 May 2014
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Cadence SpeedBridge Adapter for Ethernet Datasheet
Format: .PDF    Date: 14 Mar 2014
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Cadence C-to-Silicon Compiler Datasheet
Format: .PDF    Date: 14 Dec 2013
Datasheet
 7
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Metric-Driven Mixed-Signal Verification Flow Datasheet
Format: .PDF    Date: 10 Oct 2013
Datasheet
 3
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Cadence Palladium XP II Verification Computing Platform Technical Brief
Format: .PDF (1MB)    Date: 09 Sep 2013
Technical Brief
 2
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Productivity, Predictability, and Use-Model Versatility: The Three Key "Care-Abouts" of Choosing Hardware-Assisted Verification White Paper
Format: .PDF    Date: 09 Sep 2013
White Paper
 1
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Cadence and STMicroelectronics Success Story
Format: .PDF    Date: 14 May 2013
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Moving to SystemC TLM for Design and Verification of Digital Hardware
Date: 13 May 2013
Article
 3
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Cadence Accelerated Verification IP for PCI Express Datasheet
Format: .PDF    Date: 10 May 2013
Datasheet
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High-Level Synthesis Skill Development Needs
Date: 04 Mar 2013
Presentation
 1
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Archived webinar: Speed Verification Turnaround by Extending MDV to TLM
Date: 15 Nov 2012
Webinar
 1
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TLM-Driven Design and Verification – Time for a Methodology Shift White Paper
Format: .PDF    Date: 26 Oct 2012
White Paper
 6
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Building Energy-Efficient ICs from the Ground Up White Paper
Format: .PDF    Date: 10 Oct 2012
White Paper
 3
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Cadence and Samsung Success Story
Format: .PDF    Date: 12 Sep 2012
Success Story
 6
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Cadence Virtual System Platform for the Xilinx Zynq-7000 All Programmable SoC Datasheet
Format: .PDF    Date: 30 Aug 2012
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High Level Synthesis for ASIC Video Processing Design
Date: 01 Aug 2012
Conference Paper
 1
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Cadence and STMicroelectronics Success Story
Format: .PDF    Date: 27 Jul 2012
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 3
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Cadence Virtual System Platform for the Xilinx Zynq-7000 EPP Datasheet
Format: .PDF    Date: 11 Jun 2012
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Extending the Metric-Driven Verification Methodology to TLM
Date: 30 Mar 2012
Article
 1
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