Cadence® Palladium® XP is the industry’s first high-performance, special-purpose verification computing platform that unifies best-in-class simulation acceleration and emulation capabilities in a single environment. With its hot-swap technology, Palladium XP delivers unparalleled productivity as users can transition among simulation, simulation acceleration, and emulation environments at runtime without re-compilation. And because it is highly scalable, both local design teams and enterprise-wide customers can tackle their system-level verification challenges with confidence as requirements change.
The Palladium XP verification computing platform combines two market-leading technologies (Palladium emulation and Incisive® Xtreme® acceleration) to deliver the best of both worlds. It transcends traditional emulation by offering flexible new use models that are simulation-like and therefore simplified. By integrating with Incisive Enterprise Manager, Palladium XP supports a metric-driven flow that accelerates verification. Incisive Enterprise Manager automates and manages the execution of regressions on an accelerated verification computing platform. Engineers can use a common verification plan and extract constraint results from multiple locations into a common database for signoff analysis.
Palladium XP can also be extended for system-level power analysis and power verification. The Palladium XP Dynamic Power Analysis (DPA) option delivers a new methodology for power budgeting by allowing users to quickly identify peak and average power of SoCs with “deep” software cycles without compromising throughput.
To improve verification throughput with scalable performance, Palladium XP offers a hybrid environment that connects to real-world stimulus through a target or tester and virtual or transaction-based acceleration models. Palladium XP enables various models to be linked, compiled, and/or physically connected.
It also enables reuse of abstracted models such as C/C++, transaction-level models (TLMs), behavioral RTL, RTL/gate-level netlist, silicon/FPGA/software IP, and system-level interfaces. This unification of use modes and abstraction support gives users the flexibility to select the highest performing available IP to integrate hardware and software and significantly improve verification throughput.
- Unparalleled operational efficiency and user flexibility with highly scalable systems
- Delivers high performance of up to 4MHz
- Allows flexible configurations from 4 million gates to 2 billion gates
- Supports up to 512 users simultaneously
- Improves power efficiency compared to Palladium III by 44%
- Advanced compiler and runtime capabilities
- Hot-swap capability boosts runtime predictability
- Integrates seamlessly with Incisive products
- Built-in Xccelerator Emulator (UXE) compiler improves compile time
- Offers a unified, advanced debug environment for HW/SW co-verification
- Supports SCE-MI and SystemVerilog DPI for third-party models/tools integration
- In-Circuit Acceleration support for both static and dynamic environments
- Unique platform extensions
- Supports metric-driven verification acceleration
- Supports industry-standard hardware design and verification languages and the Universal Verification Methodology
- Enables Dynamic Power Analysis and verification by integrating with the Encounter® RTL Compiler power estimation engine
- SystemC®-to-emulation flow allows users to integrate high-level abstraction models into the system verification environment
- Integrates with the comprehensive SpeedBridge® family of rate adapters and the Cadence Verification IP portfolio