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Cadence Palladium Hybrid 


Cadence Palladium XP II and Virtual System Platform Hybrid Solution with Software Integrator

60X speed-up of OS boot over in-circuit emulation for pre-silicon software validation

The Cadence® Palladium® Hybrid solution integrates a high-performance transaction-level model of the CPU subsystem running on Cadence Virtual System Platform (VSP) with register-transfer level (RTL) for the rest of the SoC running on the Palladium platform. The solution accomplishes this by using Cadence’s exclusive Software Integrator technology to provide cross-domain memory coherency. This solution enables the software to execute at virtual platform speeds (typically between 50 – 100MIPS) and interact with the RTL of the design. The Cadence Palladium Hybrid tool also maintains memory coherency between the RTL and virtual domains, delivering 60X improvement in operating system (OS) boot and 10X improvement in post-boot software execution.

With the Cadence Palladium Hybrid solution, you can start software validation up to six months earlier in the design cycle as a result of the fast compile and turnaround times the platform offers. This can typically provide a six-month head start on software validation, which can begin prior to the RTL code freeze where typical FPGA prototyping usually starts.

Accelerating Embedded Software Development Earlier in Design Cycle
ARM and Cadence have teamed up to accelerate embedded software development earlier in the design cycle. Using Cadence® Palladium® Hybrid technology and ARM® Fast Models, ARM achieved a 50X faster OS boot-up during the development of its ARM Mali™-T760 GPU.

Compared to the previous emulation-only solution, the combination of Palladium Hybrid technology and ARM Fast Models resulted in an up to 10X speed-up of overall hardware-software testing, reducing ARM’s time from OS boot-up to test from hours to minutes while also improving turnaround time and system quality. This development speed gain boosts the ARM Mali Midgard architecture into a new era of energy efficiency.

Features/Benefits
  • High-performance software execution: Effective software execution speeds which exceed those of standalone emulation and, for certain use cases such as booting an operating system and executing graphics tests, outperform FPGA prototypes
  • Early software validation: This combination can be applied soon after enough RTL is available, enabling an early start of the software and SoC validation processes
  • Hardware / software debug: Excellent hardware and software debug capabilities are available concurrently during runtime, allowing efficient debug of complex hardware/software interaction issues
  • Increased validation throughput: This results from combining early validation start, shorter software-driven test runtime, better hardware/software debug, and increased number of concurrent users per emulator
  • Accelerated embedded software development: ARM and Cadence have partnered to accelerate embedded software development earlier in the design cycle

 

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