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Cadence Palladium Dynamic Power Analysis

System-level dynamic power analysis and power/performance tradeoffs

Palladium Dynamic Power Analysis enables SoC designers to intelligently identify, capture, and analyze power switching activity for peak and average power analysis.

Palladium Dynamic Power Analysis Datasheet »

Cadence® Palladium® Dynamic Power Analysis (DPA) uniquely enables engineers using emulation to also analyze software in a system-level environment. The solution’s ability to run various design or implementation scenarios--and determine their impact on power dissipation under a realistic application environment--is vital to striking a balance between power budget and expected performance. Additionally, the solution delivers power calculation by capturing the necessary power activities in a common DPA power database. This capability further enables the sharing of verification resources while DPA is computing the power profile offline.

Features/Benefits

Supports both RTL and gate-level power estimation
Enables high-performance system-level power estimation to identify peaks and calculate averages on long runs
Realistic in-circuit emulation environment allows users to estimate power under real operating conditions
Detailed analysis helps users identify where analysis is needed
Enables relative compare of IP at the RTL phase to identify architectural issues and offer HW/SW trade-offs
Reduces packaging cost and helps to avoid costly respins
Supports the Common Power Format (CPF)