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System Design and Verification
Hardware/software co-verification
For effective system-level verification, engineers require a high-performance environment that allows access to hardware and software debuggers while running various system-level scenarios using firmware, drivers, operating systems, and application software. Conventional simulation of designs at RTL with embedded software at the system level is impractical and has performance limitations. Offering higher throughput, superior hardware/software debug, and fast compilation, the Cadence® System Development Suite allow software developers to run and debug their designs on top of a set of open, connected, and scalable platforms.
Rapid Prototyping Platform
Part of the Cadence System Development Suite. Delivers an FPGA-based prototyping solution with a family of high-capacity FPGA boards and within a complete implementation and debug software flow. Enables early software development and high-performance system validation.
Learn more
»
Virtual System Platform
Part of the Cadence System Development Suite. Automates the process of creating and modeling virtual prototypes, debugging software, and deploying virtual prototypes to the software team. Enables software development to begin months earlier.
Learn more
»
Palladium XP Verification Computing Platform
A state-of-the-art hardware/software verification computing platform that unifies best-in-class acceleration and emulation capabilities in a single environment to boost verification throughput and productivity.
Learn more
»
Palladium series
Offers the industry’s most scalable, highest-throughput, multi-user acceleration and emulation platform. Enables designers to rapidly emulate a system-level design environment. Provides early access to hardware/software co-verification and validation months ahead of committing to silicon tapeout.
Learn more
»
Palladium Dynamic Power Analysis
Extends the Palladium accelerator/emulator with capabilities to perform system-level dynamic power analysis (DPA). By allowing engineers performing emulation to also analyze software in a realistic system-level environment, the DPA solution enables more optimal tradeoffs between power and performance.
Learn more
»
Incisive Software Extensions
Provides the productivity, predictability, and quality benefits of metric-driven techniques for hardware/software co-verification, unified hardware/software debugging, and embedded software tracing technology. Leverages and extends existing Incisive verification environment for software running on any processor.
Learn more
»
Virtual prototyping
Product delivery schedules for today’s mobile multimedia devices—with their increasing amount of software content—require design teams to begin software development concurrently or before hardware components have been completed. Virtual prototypes allow users to begin software development earlier than with FPGA or silicon prototypes, but engineers need a more efficient, automated solution than what is available today. Cadence system development technology includes a virtual prototyping solution for pre-RTL software development, functional verification, and system analysis and optimization.
Virtual System Platform
Part of the Cadence System Development Suite. Automates the process of creating and modeling virtual prototypes, debugging software, and deploying virtual prototypes to the software team. Enables software development to begin months earlier.
Learn more
»
System simulation and analysis
To ensure correct system functionality, design and verification teams must simulate, debug, verify, and analyze system hardware and software in-parallel under all expected and unexpected conditions—pre-silicon. Using Cadence
®
system simulation and analysis, engineers can perform thorough plan- and metrics-driven hardware/software co-verification at the transaction level using mixed HDLs together with SystemC
®
.
With the most comprehensive support for the latest industry standards—OSCI
®
TLM 1.0/2.0 (transaction-level modeling), IEEE 1850 PSL (assertion-based verification), and SCE-MI 2.0 (transaction-based acceleration)—engineers can apply the full breadth of Incisive
®
verification capabilities to SystemC and mixed-HDL designs across both hardware-based and software-based simulation environments. Advanced SystemC simulation features including save/restore, transaction-level recording, and multi-language hierarchical visualization/analysis to maximize engineering productivity for hardware-software debugging, verification, and validation.
Rapid Prototyping Platform
Part of the Cadence System Development Suite. Delivers an FPGA-based prototyping solution with a family of high-capacity FPGA boards and within a complete implementation and debug software flow. Enables early software development and high-performance system validation.
Learn more
»
Virtual System Platform
Part of the Cadence System Development Suite. Automates the process of creating and modeling virtual prototypes, debugging software, and deploying virtual prototypes to the software team. Enables software development to begin months earlier.
Learn more
»
Palladium XP Verification Computing Platform
A state-of-the-art hardware/software verification computing platform that unifies best-in-class acceleration and emulation capabilities in a single environment to boost verification throughput and productivity.
Learn more
»
Palladium series
Offers the industry’s most scalable, highest-throughput, multi-user acceleration and emulation platform. Enables designers to rapidly emulate a system-level design environment. Provides early access to hardware/software co-verification and validation months ahead of committing to silicon tapeout.
Learn more
»
Palladium Dynamic Power Analysis
Extends the Palladium accelerator/emulator with capabilities to perform system-level dynamic power analysis (DPA). By allowing engineers performing emulation to also analyze software in a realistic system-level environment, the DPA solution enables more optimal tradeoffs between power and performance.
Learn more
»
Incisive Enterprise Simulator
Performs multi-language coverage-driven functional verification, analysis, and debug from system level to gate level. Automates testbench generation.
Learn more
»
Incisive Software Extensions
Provides the productivity, predictability, and quality benefits of metric-driven techniques for hardware/software co-verification, unified hardware/software debugging, and embedded software tracing technology. Leverages and extends existing Incisive verification environment for software running on any processor.
Learn more
»
Metric-driven verification
One of the most critical milestones engineers must achieve during system-level verification is determining when they are done validating and verifying their design. Cadence
®
metric-driven verification not only tells engineers when they have achieved the complete coverage necessary to verify their design is correct, but it also helps them verify that the hardware and software is interacting properly per the system-level specification. With automated verification solutions that utilize metrics, engineers can significantly increase productivity and quality of block- and sub–system-level hardware verification.
System-level metric-driven verification
Learn more
»
Accelerated VIP
Learn more
»
Virtual System Platform
Part of the Cadence System Development Suite. Automates the process of creating and modeling virtual prototypes, debugging software, and deploying virtual prototypes to the software team. Enables software development to begin months earlier.
Learn more
»
Palladium XP Verification Computing Platform
A state-of-the-art hardware/software verification computing platform that unifies best-in-class acceleration and emulation capabilities in a single environment to boost verification throughput and productivity.
Learn more
»
Palladium series
Offers the industry’s most scalable, highest-throughput, multi-user acceleration and emulation platform. Enables designers to rapidly emulate a system-level design environment. Provides early access to hardware/software co-verification and validation months ahead of committing to silicon tapeout.
Learn more
»
Palladium Dynamic Power Analysis
Extends the Palladium accelerator/emulator with capabilities to perform system-level dynamic power analysis (DPA). By allowing engineers performing emulation to also analyze software in a realistic system-level environment, the DPA solution enables more optimal tradeoffs between power and performance.
Learn more
»
Incisive Enterprise Manager
Automates and guides verification from planning to closure. Includes SystemVerilog and e functional coverage capabilities.
Learn more
»
High-level synthesis
To achieve a 10-fold leap in productivity, system design and verification engineers must begin designing at a higher level of abstraction. Using Cadence
®
high-level synthesis, teams automatically generate high-quality RTL code for their application with as little as 10% of the manual effort.
TLM-Driven Design and Verification Methodology
Learn more
»
C-to-Silicon Compiler
Next-generation high-level synthesis technology automatically generates synthesizable Verilog RTL from timed or untimed C/C++/SystemC. Delivers the highest code quality in terms of area and performance.
Learn more
»
Assertion-based verification
To boost verification productivity and enhance debug visibility, system design and verification teams require an assertion-based verification environment that unifies software, languages, IP, debug, and coverage. Cadence
®
assertion-based verification enables the detection of bugs close to the source during various design phases. Cadence technologies for simulation, acceleration, emulation, verification planning and management, comprehensive coverage, and formal verification enable assertion-based verification.
The Open Verification Library (OVL) and the Incisive Assertion Library are supported along with SVA and PSL languages in various Cadence Incisive
®
verification technologies. SVA and PSL can represent very complex temporal conditions in a concise manner and they work seamlessly in simulation, acceleration, and emulation. With broad support for industry-standard languages and libraries, Cadence assertion-based verification technologies help teams achieve verification completeness and measure it against comprehensive coverage. Assertions can also serve the purpose of documentation, which is helpful when reusing IP from one project to another.
Synthesizable testbenches and in-circuit emulation using
SpeedBridge
®
Adapters
are common use modes when Palladium accelerators and emulators can be used. These use modes allow customers to run long system-level tests with high performance. Assertions are very useful during these long tests because they constantly monitor the design behavior, thus increasing debug productivity and the predictability of the design state.
Palladium series
Offers the industry’s most scalable, highest-throughput, multi-user acceleration and emulation platform. Enables designers to rapidly emulate a system-level design environment. Provides early access to hardware/software co-verification and validation months ahead of committing to silicon tapeout.
Learn more
»
Palladium Dynamic Power Analysis
Extends the Palladium accelerator/emulator with capabilities to perform system-level dynamic power analysis (DPA). By allowing engineers performing emulation to also analyze software in a realistic system-level environment, the DPA solution enables more optimal tradeoffs between power and performance.
Learn more
»
Incisive Enterprise Manager
Automates and guides verification from planning to closure. Includes SystemVerilog and e functional coverage capabilities.
Learn more
»
Verification IP integration
To ensure correct system verification, engineers must drive stimulus matching the specific protocols interfacing with their designs and check the design response. They must also test the interface protocols under real-world operating conditions. Integrating Cadence® verification IP, engineers can rapidly construct a complete system verification environment for both acceleration and emulation.
New Verification IP integration
Incisive System-Level Verification IP
Incisive System-Level Verification IP includes the following groups of models:
Transaction-based acceleration (TBA) VIP
provides off-the shelf transactors for protocols driven by SystemC or e testbenches with the Palladium series.
Assertion-based acceleration (ABA) VIP
provides protocol monitors that can be incorporated into Incisive acceleration/emulation environments with Palladium systems.
Learn more
»
Incisive Memory Models for Emulation
Cadence provides a wide range of Incisive memory models used for emulation and acceleration. These memory models can be compiled and physically mapped into the emulator or accelerator along with the customer's design. Cadence supplies the most common memory models such as SRAM DDR, SRAM QDR, DDR SDRAM, FCRAM, CellularRAM, SPI Memory, Asynchronous RAM, and Flash memory.
Learn more
»
Palladium XP Verification Computing Platform
A state-of-the-art hardware/software verification computing platform that unifies best-in-class acceleration and emulation capabilities in a single environment to boost verification throughput and productivity.
Learn more
»
Cadence SpeedBridge Adapters
Enables a full-speed device to interface directly with a design running at emulation speed. Supports in-circuit emulation under real-world operating conditions. Reduces risk by enabling the emulator to leverage stimuli and responses from external sources that ensure the design’s correct in-system behavior.
Learn more
»
Simulation acceleration
While software simulators offer flexible verification environments at the module and block levels, their throughput degrades as designers migrate to system-level verification with larger design sizes. This gap widens when running long sequential tests or embedded software use cases.
Cadence
®
simulation acceleration technology allows designers to reuse the existing simulation verification environment and accelerate it far beyond software simulator speed at both RTL and gate levels. It also offers both signal-based acceleration (SBA) and advanced transaction-based acceleration (TBA) methodologies to further increase performance. SBA allows users to accelerate the existing software simulator verification environment without changes to the existing methodology or testbench environment. TBA enables the simulation environment to run up to full emulation speed while maintaining the flexibility and testbench reuse of the simulation environment. The Cadence accelerated verification intellectual property (VIP) library provides off-the-shelf transactors for the most common protocols.
Transaction-based acceleration
Learn more
»
Accelerated VIP
Learn more
»
Palladium XP Verification Computing Platform
A state-of-the-art hardware/software verification computing platform that unifies best-in-class acceleration and emulation capabilities in a single environment to boost verification throughput and productivity.
Learn more
»
Palladium series
Offers the industry’s most scalable, highest-throughput, multi-user acceleration and emulation platform. Enables designers to rapidly emulate a system-level design environment. Provides early access to hardware/software co-verification and validation months ahead of committing to silicon tapeout.
Learn more
»
Palladium Dynamic Power Analysis
Extends the Palladium accelerator/emulator with capabilities to perform system-level dynamic power analysis (DPA). By allowing engineers performing emulation to also analyze software in a realistic system-level environment, the DPA solution enables more optimal tradeoffs between power and performance.
Learn more
»
Incisive Software Extensions
Provides the productivity, predictability, and quality benefits of metric-driven techniques for hardware/software co-verification, unified hardware/software debugging, and embedded software tracing technology. Leverages and extends existing Incisive verification environment for software running on any processor.
Learn more
»
Low-power verification and analysis
To verify that complex system-level designs are optimized for low power, engineers need an automated process for identifying bugs and ensuring that all power-related logic is exercised. Cadence
®
low-power verification and analysis technology delivers the industry's first complete flow that integrates logic design, verification, and implementation technologies with the Common Power Format (CPF). During the system verification process, engineers can use the flow with Cadence emulation technology to further enhance productivity and predictability.
Palladium XP Verification Computing Platform
A state-of-the-art hardware/software verification computing platform that unifies best-in-class acceleration and emulation capabilities in a single environment to boost verification throughput and productivity.
Learn more
»
Palladium series
Offers the industry’s most scalable, highest-throughput, multi-user acceleration and emulation platform. Enables designers to rapidly emulate a system-level design environment. Provides early access to hardware/software co-verification and validation months ahead of committing to silicon tapeout.
Learn more
»
Palladium Dynamic Power Analysis
Extends the Palladium accelerator/emulator with capabilities to perform system-level dynamic power analysis (DPA). By allowing engineers performing emulation to also analyze software in a realistic system-level environment, the DPA solution enables more optimal tradeoffs between power and performance.
Learn more
»
Incisive Enterprise Simulator
Performs multi-language coverage-driven functional verification, analysis, and debug from system level to gate level. Automates testbench generation.
Learn more
»
Cadence Low-Power Methodology Kit
Streamlines the adoption of low-power techniques and optimizes their usage. Eliminates risk with a complete front-to-back methodology, best practices, checklists, and reference flows.
Learn more
»
Emulation
To undertake comprehensive system-level verification, engineers must stress and validate their design in a scalable verification environment—one that offers a high degree of control and visibility, applies system-level stimulus to the design, and verifies the performance and behavior of the integrated system. Using Cadence
®
high-throughput emulation technology, design and verification teams can rapidly bring-up, verify, debug, and turnaround their hardware and software designs using realistic system-level environments.
Palladium XP Verification Computing Platform
A state-of-the-art hardware/software verification computing platform that unifies best-in-class acceleration and emulation capabilities in a single environment to boost verification throughput and productivity.
Learn more
»
Palladium series
Offers the industry’s most scalable, highest-throughput, multi-user acceleration and emulation platform. Enables designers to rapidly emulate a system-level design environment. Provides early access to hardware/software co-verification and validation months ahead of committing to silicon tapeout.
Learn more
»
Palladium Dynamic Power Analysis
Extends the Palladium accelerator/emulator with capabilities to perform system-level dynamic power analysis (DPA). By allowing engineers performing emulation to also analyze software in a realistic system-level environment, the DPA solution enables more optimal tradeoffs between power and performance.
Learn more
»
Cadence SpeedBridge Adapters
Enables a full-speed device to interface directly with a design running at emulation speed. Supports in-circuit emulation under real-world operating conditions. Reduces risk by enabling the emulator to leverage stimuli and responses from external sources that ensure the design’s correct in-system behavior.
Learn more
»
FPGA-based prototyping
Today’s electronics products are all about the software. Development costs and schedules are now dominated by software, which has become the prime differentiator. Therefore, building today’s SoCs—with their increasing amount of software content—requires design teams to start the software development process as early as possible to stay on schedule and on budget. FPGA-based prototyping has become the methodology of choice for many designers. But growing complexities and shrinking market windows are making the bring-up of such a prototyping system increasingly painful and time consuming. Using Cadence FPGA-based prototyping technology, design and verification teams can rapidly bring-up a prototype and provide a pre-silicon platform for early software development, system validation, and for running long regressions.
Rapid Prototyping Platform
Part of the Cadence System Development Suite. Delivers an FPGA-based prototyping solution with a family of high-capacity FPGA boards and within a complete implementation and debug software flow. Enables early software development and high-performance system validation.
Learn more
»
Cadence SpeedBridge Adapters
Enables a full-speed device to interface directly with a design running at emulation speed. Supports in-circuit emulation under real-world operating conditions. Reduces risk by enabling the emulator to leverage stimuli and responses from external sources that ensure the design’s correct in-system behavior.
Learn more
»
Cadence Low-Power Methodology Kit
Streamlines the adoption of low-power techniques and optimizes their usage. Eliminates risk with a complete front-to-back methodology, best practices, checklists, and reference flows.
Learn more
»
Cadence SpeedBridge Adapters
Enables a full-speed device to interface directly with a design running at emulation speed. Supports in-circuit emulation under real-world operating conditions. Reduces risk by enabling the emulator to leverage stimuli and responses from external sources that ensure the design’s correct in-system behavior.
Learn more
»
C-to-Silicon Compiler
Next-generation high-level synthesis technology automatically generates synthesizable Verilog RTL from timed or untimed C/C++/SystemC. Delivers the highest code quality in terms of area and performance.
Learn more
»
Incisive Enterprise Manager
Automates and guides verification from planning to closure. Includes SystemVerilog and e functional coverage capabilities.
Learn more
»
Incisive Enterprise Simulator
Performs multi-language coverage-driven functional verification, analysis, and debug from system level to gate level. Automates testbench generation.
Learn more
»
Incisive Software Extensions
Provides the productivity, predictability, and quality benefits of metric-driven techniques for hardware/software co-verification, unified hardware/software debugging, and embedded software tracing technology. Leverages and extends existing Incisive verification environment for software running on any processor.
Learn more
»
Palladium Dynamic Power Analysis
Extends the Palladium accelerator/emulator with capabilities to perform system-level dynamic power analysis (DPA). By allowing engineers performing emulation to also analyze software in a realistic system-level environment, the DPA solution enables more optimal tradeoffs between power and performance.
Learn more
»
Palladium series
Offers the industry’s most scalable, highest-throughput, multi-user acceleration and emulation platform. Enables designers to rapidly emulate a system-level design environment. Provides early access to hardware/software co-verification and validation months ahead of committing to silicon tapeout.
Learn more
»
Palladium XP Verification Computing Platform
A state-of-the-art hardware/software verification computing platform that unifies best-in-class acceleration and emulation capabilities in a single environment to boost verification throughput and productivity.
Learn more
»
Rapid Prototyping Platform
Part of the Cadence System Development Suite. Delivers an FPGA-based prototyping solution with a family of high-capacity FPGA boards and within a complete implementation and debug software flow. Enables early software development and high-performance system validation.
Learn more
»
Virtual System Platform
Part of the Cadence System Development Suite. Automates the process of creating and modeling virtual prototypes, debugging software, and deploying virtual prototypes to the software team. Enables software development to begin months earlier.
Learn more
»
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Hardware/Software Verification with Incisive Software Extensions Technical Paper
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