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System Design and Verification 

Press Releases
Faraday Reduces Packaging Design Time by 60 Percent Using Cadence OrbitIO Interconnect Designer and SiP Layout
Media Alert: Connect, Share, and Inspire at CDNLive EMEA 2016—Cadence User Conference
Cadence Digital and Signoff Tools Certified on Samsung Foundry’s 14LPP Process

Articles
More Test Needed For Integrated IP
A return to EDA and a Renewed Commitment to High-Level Synthesis
Analysis of HLS Results Made Easier

Events
Cadence Club Verification
05/16/2016 - Dan Accadia Hotel, Herzelia
Design Automation Conference - DAC 2016
06/05/2016 - Austin
CDNLive Korea 2016
07/13/2016 - Seoul

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