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System Design and Verification 

Press Releases
Cadence Introduces Genus Synthesis Solution, Delivering Up to 10X Improvement in RTL Design Productivity
Cadence Announces First Quarter 2015 Financial Results Webcast
Fujitsu Kansai-Chubu Net-Tech Shortens Design Time by 40 Percent on 100G Transport System with Cadence High-Level Synthesis Solution

Articles
More Test Needed For Integrated IP
A return to EDA and a Renewed Commitment to High-Level Synthesis
Analysis of HLS Results Made Easier

Events
CDNLive Boston
09/02/2015 - Boston
CDNLive Korea
09/17/2015 - Seoul
Jasper User Group Conference 2015
10/07/2015 - San Jose

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