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Incisive Software Extensions 

Advanced verification and unified debugging of hardware and software

Increase hardware/software bring-up productivity and system quality using Incisive Software Extensions to apply testbench automation and unify hardware/software debug windows, breakpoints, and single-step execution control.

Hardware/Software Verification with Incisive Software Extensions Technical Paper »
32 resources found
 
Title Type Rated
Enterprise System-Level (ESL) Verification Solution Beyond "First Silicon Success" White Paper
Format: .PDF    Date: 15 Dec 2011
 		White Paper
 3
Recommend!
Power-Aware Verification Spans IC Design Cycle White Paper
Format: .PDF    Date: 12 Dec 2011
 		White Paper
 18
Recommend!
Mixed Signal Verification of Dynamic Adaptive Power Conference Paper Presented at DVCon 2010
Format: .PDF (1.2MB)    Date: 11 Mar 2010
 		Conference Paper
 2
Recommend!
Apples versus Apples HVL Comparison Finally Arrives Conference Paper Presented at DVCon 2010
Format: .PDF    Date: 11 Mar 2010
 		Conference Paper
 2
Recommend!
Where OOP Falls Short of Hardware Verification Needs Conference Paper Presented at DVCon 2010
Format: .PDF    Date: 11 Mar 2010
 		Conference Paper
 2
Recommend!
Metric-Driven Verification Ensures Software Development Quality White Paper
Format: .PDF    Date: 18 May 2009
 		White Paper
 4
Recommend!
Interview: Verification Planning and Management Methodology Focuses on All the Right Things
Format: .PDF    Date: 24 Mar 2008
 		Cadence Article
 6
Recommend!
Interview: By Popular Demand—SystemVerilog Open Verification Methodology
Format: .PDF    Date: 10 Jan 2008
 		Release Information
 3
Recommend!
Interview: Closing in on Profitability with Leading-Edge Verification Practices
Format: .PDF    Date: 05 Dec 2007
 		Cadence Article
 0
Recommend!
Integrating Design IP and Verification IP to Ensure Quality and Predictability
Format: .PDF (1.3MB)    Date: 17 Oct 2007
 		Conference Paper
 0
Recommend!
Developing a Gigabit Ethernet VIP Using The Plan-to-Closure Methodology Featuring SystemVerilog
Format: .PDF    Date: 17 Oct 2007
 		Conference Paper
 0
Recommend!
Modeling for Stimulus Generation, EZ-start Guide
Format: .PDF    Date: 16 Oct 2007
 		Application Brief
 0
Recommend!
Coverage-Driven AMS Verification of a 4Mb Z-RAM Macro
Format: .PDF    Date: 16 Sep 2007
 		Conference Paper
 1
Recommend!
Implementing an Automated Checking Scheme for a Video-Processing Device
Format: .PDF    Date: 15 Sep 2007
 		Conference Paper
 0
Recommend!
Functional Closure using the Plan-to-Closure Methodology
Format: .PDF (1.3MB)    Date: 15 Sep 2007
 		Conference Paper
 0
Recommend!
Plan-to-Silicon: Functional Test Automation using the Incisive Platform and Plan-to-Closure Methodology
Format: .PDF    Date: 15 Sep 2007
 		Conference Paper
 0
Recommend!
Building a SystemVerilog Universal Verification Component with the Incisive Plan-to-Closure Methodology
Format: .PDF (1.5MB)    Date: 15 Sep 2007
 		Conference Paper
 0
Recommend!
Module- or Class-Based URM? A Pragmatic Guide to Creating Verification Environments in SystemVerilog
Format: .PDF    Date: 15 Sep 2007
 		Conference Paper
 1
Recommend!
Verification Test Sequence Reuse from Block to System within Incisive Plan-to-Closure Methodology
Format: .PDF    Date: 15 Sep 2007
 		Conference Paper
 0
Recommend!
Developing a Gigabit Ethernet VIP Using the Plan to Closure Methodology Featuring SystemVerilogpdf
Format: .PDF    Date: 30 Jul 2007
 		Technical Paper
 2
Recommend!
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