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Incisive Enterprise Simulator 

Multi-language simulation fuels testbench automation, low-power, metric driven verification, and mixed-signal verification

Incisive Enterprise Simulator (IES) provides the most comprehensive IEEE language support with unique capabilities supporting the intent, abstraction, and convergence needed to speed silicon realization. IES is the core engine for low-power verification working closely with Conformal LP, the digital engine for mixed-signal verification working with Virtuoso simulators, the testbench engine for simulation acceleration with Xtreme and Palladium, and the RTL engine working with TLM verification solutions.

Incisive Metrics Center Technical Brief »
Incisive Enterprise Simulator Datasheet »
Cadence Export Model Packager Datasheet »
Hardware Simulator Performance Scaling to Meet Advanced Node SoC Verification Requirements Technical Paper »
52 resources found
 
Title Type Rated
Cadence and STMicroelectronics Success Story
Format: .PDF    Date: 14 May 2013
 		Success Story
 0
Recommend!
Cadence and RivieraWaves Success Story
Format: .PDF    Date: 27 Mar 2013
 		Success Story
 0
Recommend!
Incisive Metrics Center Technical Brief
Format: .PDF    Date: 01 Feb 2013
 		Technical Brief
 0
Recommend!
Cadence Incisive Enterprise Simulator and Samsung Success Story
Format: .PDF    Date: 14 Nov 2012
 		Success Story
 0
Recommend!
Cadence and STMicroelectronics Success Story II
Format: .PDF    Date: 27 Jul 2012
 		Success Story
 3
Recommend!
Cadence and Silicon Laboratories Success Story
Format: .PDF    Date: 11 Jul 2012
 		Success Story
 5
Recommend!
Cadence and Xilinx Success Story
Format: .PDF    Date: 11 Jul 2012
 		Success Story
 0
Recommend!
Hardware Simulator Performance Scaling to Meet Advanced Node SoC Verification Requirements Technical Paper
Format: .PDF    Date: 25 Jan 2012
 		Technical Paper
 0
Recommend!
Enterprise System-Level (ESL) Verification Solution Beyond "First Silicon Success" White Paper
Format: .PDF    Date: 15 Dec 2011
 		White Paper
 4
Recommend!
Incisive Enterprise Simulator Datasheet
Format: .PDF    Date: 14 Dec 2011
 		Datasheet
 17
Recommend!
Power-Aware Verification Spans IC Design Cycle White Paper
Format: .PDF    Date: 12 Dec 2011
 		White Paper
 20
Recommend!
Cadence and LSI Corporation Success Story
Format: .PDF    Date: 07 Dec 2011
 		Success Story
 0
Recommend!
Cadence and Siemens Sucess Story
Format: .PDF (1.5MB)    Date: 30 Nov 2011
 		Success Story
 2
Recommend!
Cadence Export Model Packager Datasheet
Format: .PDF    Date: 03 Oct 2011
 		Datasheet
 0
Recommend!
Mixed Signal Verification of Dynamic Adaptive Power Conference Paper Presented at DVCon 2010
Format: .PDF (1.2MB)    Date: 11 Mar 2010
 		Conference Paper
 2
Recommend!
Apples versus Apples HVL Comparison Finally Arrives Conference Paper Presented at DVCon 2010
Format: .PDF    Date: 11 Mar 2010
 		Conference Paper
 2
Recommend!
Where OOP Falls Short of Hardware Verification Needs Conference Paper Presented at DVCon 2010
Format: .PDF    Date: 11 Mar 2010
 		Conference Paper
 2
Recommend!
Metric-Driven Verification Ensures Software Development Quality White Paper
Format: .PDF    Date: 18 May 2009
 		White Paper
 4
Recommend!
Practical Guide to Low-Power Design - User Experience with CPF
Date: 16 May 2008
 		eBook
 41
Recommend!
Interview: Verification Planning and Management Methodology Focuses on All the Right Things
Format: .PDF    Date: 24 Mar 2008
 		Cadence Article
 6
Recommend!
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