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Incisive Enterprise Simulator 


Multi-language simulation fuels testbench automation, low-power, metric driven verification, and mixed-signal verification

Incisive Enterprise Simulator (IES) provides the most comprehensive IEEE language support with unique capabilities supporting the intent, abstraction, and convergence needed to speed silicon realization. IES is the core engine for low-power verification working closely with Conformal LP, the digital engine for mixed-signal verification working with Virtuoso simulators, the testbench engine for simulation acceleration with Xtreme and Palladium, and the RTL engine working with TLM verification solutions.

Incisive Metrics Center Technical Brief »
Incisive Enterprise Simulator Datasheet »
Cadence Export Model Packager Datasheet »
Hardware Simulator Performance Scaling to Meet Advanced Node SoC Verification Requirements Technical Paper »

Product Image When digital simulation became commonplace in the 1980s, flows were simple: RTL, then gate, then implement. Since then, simulation has matured into verification and has become the critical means to enable productivity, predictability, and quality in complex FPGAs, ASICs, and custom designs. As part of that maturation, what has emerged are new means for generating metrics (to measure the progress against the verification plan), new abstractions for both digital and analog simulation (to move verification earlier in the process), and new methods for speeding convergence.

Incisive Enterprise Simulator is the most used engine in the industry, continually adding new technology to support each of the verification niches that have emerged. Today, Enterprise Simulator fuels testbench automation, reuse, and analysis to verify designs from the system level, through RTL, to the gate level. It supports the metric-driven approach implemented by Incisive Enterprise Manager. Its native-compiled architecture speeds the simultaneous simulation of transaction-level, behavioral, low-power, RTL, and gate-level models—critical to the verification of modern multi-language, multi-abstraction, mixed-signal SoCs.

Enterprise Simulator simplifies the overall debugging effort and shortens debug turnaround time by separating design failures from simulation failures, sorting and grouping these failures for easy selection and action. Its comprehensive language support enables source code debug for complex mixed-language SoCs where it is critical to trace data through multiple blocks of IP to identify and fix errors. Enterprise Simulator’s integrated support for low-power, mixed-signal, and embedded software enable debug for any SoC configuration.

Cadence provides two sophisticated debug solutions to address all of your RTL, testbench, and SoC verification debug needs:
  • SimVision: a unified graphical debugging environment within Enterprise Simulator that supports signal-level and transaction-based flows across all IEEE-standard design, testbench, and assertion languages, in addition to concurrent visualization of hardware, software, and analog domains. Learn more »
  • Incisive Debug Analyzer: a new, unique, “interactive” post-process debug solution to help you debug in minutes instead of hours. Learn more »
Enterprise Simulator supports all IEEE-standard languages, the Open Verification Methodology (OVM), Accellera’s Universal Verification Methodology (UVM), and the e Reuse Methodology (eRM), making it quick and easy to integrate with your established verification flows. You can extend the functionality of Enterprise Simulator with our Virtual System Platform, which provides a high-throughput channel between the testbench and the device under test (DUT). This enables automated metric-driven verification of embedded software exactly as if it were another part of the DUT.

Benefits
  • Fuels testbench automation, analysis, and reuse for increased productivity
  • Ensures verification quality by tracking industry-standard coverage metrics including functional, transactional, low-power, and HDL code, plus automatic data and assertion checking
  • Drives and guides verification with an automatically back-annotated and executable verification plan
  • Creates reusable sequences and multi-channel virtual sequences on top of a multi-language verification environment
  • Configures existing Universal Verification Components (UVCs) or quickly constructs all-new UVCs
  • Enables advanced debug using SimVision for transaction-level models, SystemVerilog/e class libraries, and transient mixed-signal, low-power, and traditional waveform analysis
  • Supports e, Open Verification Library (OVL), OVM class library, UVM class library, SystemC™, SystemC Verification Library, SystemVerilog, Verilog, VHDL, PSL, SVA, and CPF
  • Delivers the highest possible performance across multiple levels of abstraction, supporting the ability to “hot swap” the RTL simulation in/out of the Palladium XP accelerator/emulator

 

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