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System Design and Verification  

The Challenge: An App-Driven Market
Software is eclipsing hardware as the main driver of system development cost, schedule, and risk. As software applications have become the primary product differentiator, systems and semiconductor companies must provide not only silicon, but complete hardware/software systems ready for apps deployment. EDA companies must provide solutions for both.

Productive and profitable System Realization requires a set of development platforms that is:
  • Open—to support language/protocol standards and third-party tools
  • Connected—for fast migration among platforms, tasks, and HW/SW domains
  • Scalable—for sufficient performance, capacity, and embedded software volume distribution
The Solution: A System Development Suite
The Cadence® System Development Suite accelerates system integration, validation, and bring-up with a set of four connected platforms for concurrent HW/SW design and verification. Its technologies span the entire design cycle, from early architectural-level software development through testbench simulation and system validation to prototyping. It is open for third-party integration and supports industry standards and multiple levels of design abstraction. It allows easy migration among the four platforms and between HW/SW domains. And, it can scale to meet performance, capacity, and volume needs as they expand.

Built on top of market-leading Cadence technologies—the Incisive® Verification Platform and the Palladium® XP Verification Computing Platform—the System Development Suite extends the power of familiar simulation and emulation-based environments with two new hardware-aware software development platforms. Each of the four platforms is optimized for a different part of the system development flow.

Cadence Virtual System Platform
The Virtual System Platform is a new solution for early software development at the architectural and prototype design phases. It provides an integrated HW/SW debug environment with unique multi-core capabilities, it is connected to the RTL verification flow, and it automates and accelerates the creation of new transaction-level models (TLMs). While ideal for pre-RTL, architectural-level software development, the Virtual System Platform can also be used in a post-RTL mode to generate virtual prototypes that provide an alternative to reference boards.
  • Based on SystemC® TLM 2.0 and IEEE 1666 standard
  • Supports third-party processor models (ARM® Fast Models, Imperas OVP models)
  • Supports third-party software debuggers (ARM, Lauterbach, GDB)
  • Scales from single-core to multi-core software development and debug with performance reaching hundreds of MHz
Cadence Incisive Verification Platform
Well-known for many years, the Incisive Verification Platform is a complete family of tools optimized for block- and chip-level verification with testbench simulation as a focal point. It also includes technologies for verification planning and management, verification IP creation and reuse, mixed-signal simulation, and formal analysis. Incisive Software Extensions generate a system testbench with access to the software executing on processor models, thus allowing software driver verification. The Incisive Verification Platform also provides a metric-driven verification flow, which starts with an executable verification plan, collects and analyzes coverage metrics, and makes changes as needed to reach closure.
  • Supports e, SystemC, and SystemVerilog languages
  • Supports the acceleration-ready Universal Verification Methodology (UVM)
  • Provides the SimVision debug user interface used by all other Platforms in the Suite
  • Supports a mixed-signal environment
Cadence Verification Computing Platform
The Verification Computing Platform (Palladium XP) performs advanced simulation acceleration and emulation in a single environment, with hot-swap capability for instant migration among tasks. Ideal for long regression tests and system validation, it performs HW/SW co-verification and offers flexible support for hard/soft IP. The Verification Computing Platform’s transaction-based acceleration capabilities, combined with Accelerated Verification IP, speed up a metric-driven UVM-based verification flow through multiple interfaces and third-party tools. Cadence SpeedBridge® Adapters allow connections to real-world hardware for in-circuit emulation.
  • Supports e, SystemC, and SystemVerilog languages, the UVM, and Accellera SCE-MI
  • Offers configurations up to 2 billion gates and up to 4 MHz speed
  • Supports dynamic power analysis and low-power verification
  • Supports up to 512 simultaneous users with a granularity of 4M gates
Cadence Protium Rapid Prototyping Platform
A new generation of the popular Rapid Prototyping Platform is now available. Like its predecessor, the Cadence Protium™ rapid prototyping platform combines high-capacity FPGA boards with a complete implementation and debug software flow. Ideal for exhaustive regression tests and cycle-accurate software development, the Protium platform shortens bring-up time, automates multi-FPGA partitioning, and includes a powerful debug capability.
  • Delivers fast compilation and partitioning, supporting up to 75 million gates/hour
  • Reduces prototype bring-up time by up to 70%, thereby shortening the process from months to weeks
  • Supports up to 100 million gates, which is a 4X increase in capacity compared to its predecessor
  • Supports standard interfaces (PCI Express®, Ethernet, USB) and Cadence SpeedBridge® Adapters
  • Maintains compatibility with the Palladium XP verification computing platform

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