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System Design and Verification 

Press Releases
Fujitsu Kansai-Chubu Net-Tech Shortens Design Time by 40 Percent on 100G Transport System with Cadence High-Level Synthesis Solution
Cadence Perspec System Verifier Delivers Up to 10X Productivity Improvement in System-on-Chip Verification
Media Alert: Cadence to Showcase Latest Automotive Technologies at the 2014 IEEE-SA Ethernet & IP @ Automotive Technology Day

Articles
More Test Needed For Integrated IP
A return to EDA and a Renewed Commitment to High-Level Synthesis
Analysis of HLS Results Made Easier

Events
Verification Futures
02/05/2015 - Reading
DVCon 2015
03/02/2015 - DoubleTree Hotel, San Jose
CDNLive Silicon Valley 2015
03/10/2015 - San Jose

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