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System Design and Verification

AMD AMD Alex Starr Alex Starr, Hardware Emulation Architect at AMD, highlights the unique capabilities of Palladium XP and in-circuit acceleration

Broadcom Vahid Ordoubadian Broadcom Vahid Ordoubadian, Director - Mobile Platform Group at Broadcom, describes the use of Cadence Palladium XP to validate a new architecture for a complex mobile SoC for mobile platform devices.

Agere Systems

Design Challenge
	Adopt a new verification environment to enable hardware/software co-verification
	Speed development time for 6-million-gate Link Layer Processor
Cadence Solution
	Demonstrated the power of the Cadence Palladium® accelerator/ emulator by bringing up a new verification environment in only two weeks
	Success of initial project convinced Agere to choose the Incisive Palladium II system for future designs
Read Full story»

Anchor Bay

Design Challenge
	Larger chips but shorter design cycles
	Integrating an entire transceiver supporting multiple standards onto a single SoC
Cadence Solution
	Cadence Incisive Xtreme III boosts design team verification productivity with instant "hot swap" among simulation, acceleration, and emulation
Read Full story»

Casio

Design Challenge
	Migrate Casio engineers to a new transaction-level modeling (TLM)-driven design methodology based on next-generation high-level synthesis (HLS)
	Rearchitect legacy designs to maximize the benefit of new process technologies, while avoiding the effort of developing new RTL manually from scratch
Cadence Solution
	R&D partnership with Casio engineers to adopt next-generation HLS technology developed at Cadence for production usage at Casio
	Comprehensive design and verification methodologies/flows (specified and developed with Casio engineers) to integrate HLS with the rest of Casio production design flows
Read Full story»

Nufront

Business Challenges
	Quickly roll out a third-generation dualcore Cortex-A9 mobile computing chip without sacrificing quality
	Enable customers to speed up product launches and win more business
Design Challenges
	Design a complex chip with 12M gates
	Comply with strict mobile-computing platform requirements
	Achieve low levels of power consumption and a high level of performance
Cadence Solutions
	Palladium XP Verification Computing Platform
	Incisive Enterprise Manager
	Palladium XP Dynamic Power Analysis
	SpeedBridge rate adapters
Results
	Sped up simulation goals by approximately 1,000x
	Increased productivity while meeting stringent quality requirements
Read Full story»

NVIDIA Narendra Konda NVIDIA Narendra Konda, Director of Hardware Engineering at NVIDIA, outlines how the Cadence System Development Suite helps his design team successfully integrate complex hardware and software, develop app-ready systems more quickly, and ultimately improve the overall quality and competitiveness of their products.

Philips

Design Challenge
	Adopt a new process that would allow the team to achieve higher productivity without disrupting their existing design flow
Cadence Solution
	Deployed the Cadence Incisive® Xtreme® Server, an easy-to-use solution that integrated seamlessly into the team's existing SoC design flow
Read full story »

Silicon Laboratories

Design Challenge
	Full-chip verification was much too slow with regard to integrating the analog and digital content at the full chip level
	Verification productivity must be improved by allowing users to begin the digital verification effort much sooner in the overall process
Cadence Solution
	Cadence Incisive Enterprise Simulator running the Digital Mixed Signal option
	Cadence Mixed-Signal Solution allows users to seamlessly connect Real Value Models to the digital content
Read Full story»

Sound Design

Design Challenge
	Develop the industry’s first monolithic, 4-core audio aid
	Shrink the die size to meet a 3.8mm limit for the human ear
	Meet ultra-low power targets with customized clock timing and advanced chip stacking
Cadence Solution
	Provide a complete, production-proven, advanced digital design, implementation, and verification flow
	Mitigate risk and optimize time to productivity with expert design consulting services
Read Full story»

STMicroelectronics

Design Challenge
	Verify a 100-million-transistor IC on a tight schedule using existing verification environment
Cadence Solution
	HW-based verification system
Read full story »

STMicroelectronics

Business Challenge

Achieve faster debug of RTL data cache flow
Quickly gain familiarity with new testbench for enhanced productivity

Design Challenges

Learn testbench environment and manage debug process independently after support from testbench developer ended
Detect and resolve bugs faster and earlier in the process

Cadence Solutions

Incisive Debug Analyzer
Incisive Specman Elite Testbench
Incisive Enterprise Simulator
SimVision

Results

Saved 2 months of debugging time
Enhanced team productivity with easy-to-use debug tool

Read full story»

STMicroelectronics Laurent Mailet-Contoz STMicroelectronics Laurent Mailet-Contoz, Project Leader from STMicroelectronics uses the Incisive verification platform at the transaction level to reduce their design cycle and help the company to be the first to new markets.

Sun Microsystems

Design Challenge
	Develop the highest throughput and most eco-responsible processor available
	Employ a verification platform that could eliminate costly respins and accelerate project completion
Cadence Solution
	Seamlessly integrated simulation, acceleration, and in-circuit emulation into a single verification environment
Read full story »

Sun Microsystems Jai Kumar Sun Microsystems Jai Kumar, Verification Technologist from Sun Microsystems shared his verification experience of advanced development of UltraSPARC processors with Cadence Incisive Xtreme series.

Texas Instruments

Business Challenge
	Short time-to-market window for complex mixed-signal design verification
Design Challenges
	High-performance, ultra low-power features in close interaction with core analog functional blocks at the SoC level
	High-volume product
	Functional failures would lead to costly design iterations
Cadence Solutions
	Digital-centric mixed-signal verification flow
	Incisive Enterprise Simulator Digital/Mixed-Signal (DMS) Option
	Incisive Enterprise Specman Elite Testbench
	Incisive Enterprise Manager
	Virtuoso AMS Designer with flexible analog simulation
	Virtuoso Accelerated Parallel Simulator – XL
	Customer Support
Results
	300x faster verification vs. mixed-signal simulation at the transistor level
	Improved time to market and product quality with mixed-signal regression runs
	Fewer re-spins with high-performance, real-number modeling and top-level, metric-driven mixed-signal SoC verification
	Earlier detection and correction of errors
	10x cycle-time improvement in mixed-signal verification
Read Full story»

Duolog David Murray Duolog David Murray, CTO at Duolog, discusses collaborating with Cadence to help customers address SoC integration and verification.

Freescale Semiconductor Freescale Semiconductor Wai-Chee Wong Wai-Chee Wong, Senior Member of Technical Staff at Freescale Semiconductor, details how Palladium XP helps speed their verification effort by 10,000x over simulation.

Imperas and Cadence Collaboration

Larry Lapides, Imperas and Larry Melling, Cadence
Imperas and Cadence Collaboration
Hear from Larry Lapides, Vice President of Sales at Imperas, and Larry Melling Product Manager - Virtual System Platform at Cadence, as they describe the collaboration and use of the Cadence Virtual System Platform along with Imperas’ processor models and verification analysis and profiling tools to address challenges of embedded software development for complex SOCs.

NVIDIA Narendra Konda NVIDIA Narendra Konda, Director, HW Engineering at NVIDIA, discusses leveraging Palladium XP and the Rapid Prototyping Platform to integrate complex hardware and software designs.

STMicroelectronics Abhishek Jain STMicroelectronics Abhishek Jain, Technical Manager at STMicroelectronics, talks about working with the Cadence Incisive Verification Solution to deploy a UVM multi-language, low-power verification methodology resulting in earlier and integrated verification.

Xilinx

Xilinx
David Beal
David Beal, Zynq 7000 EPP Product Manager at Xilinx, describes how the Cadence Virtual System Platform helps to accelerate product development