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System Design and Verification

Agere Systems

Design Challenge
	Adopt a new verification environment to enable hardware/software co-verification
	Speed development time for 6-million-gate Link Layer Processor
Cadence Solution
	Demonstrated the power of the Cadence Palladium® accelerator/ emulator by bringing up a new verification environment in only two weeks
	Success of initial project convinced Agere to choose the Incisive Palladium II system for future designs
Read Full story»

Anchor Bay

Design Challenge
	Larger chips but shorter design cycles
	Integrating an entire transceiver supporting multiple standards onto a single SoC
Cadence Solution
	Cadence Incisive Xtreme III boosts design team verification productivity with instant "hot swap" among simulation, acceleration, and emulation
Read Full story»

Casio

Design Challenge
	Migrate Casio engineers to a new transaction-level modeling (TLM)-driven design methodology based on next-generation high-level synthesis (HLS)
	Rearchitect legacy designs to maximize the benefit of new process technologies, while avoiding the effort of developing new RTL manually from scratch
Cadence Solution
	R&D partnership with Casio engineers to adopt next-generation HLS technology developed at Cadence for production usage at Casio
	Comprehensive design and verification methodologies/flows (specified and developed with Casio engineers) to integrate HLS with the rest of Casio production design flows
Read Full story»

NVIDIA Narendra Konda NVIDIA Narendra Konda, Director of Hardware Engineering at NVIDIA, outlines how the Cadence System Development Suite helps his design team successfully integrate complex hardware and software, develop app-ready systems more quickly, and ultimately improve the overall quality and competitiveness of their products.

Philips

Design Challenge
	Adopt a new process that would allow the team to achieve higher productivity without disrupting their existing design flow
Cadence Solution
	Deployed the Cadence Incisive® Xtreme® Server, an easy-to-use solution that integrated seamlessly into the team's existing SoC design flow
Read full story »

Silicon Laboratories

Design Challenge
	Full-chip verification was much too slow with regard to integrating the analog and digital content at the full chip level
	Verification productivity must be improved by allowing users to begin the digital verification effort much sooner in the overall process
Cadence Solution
	Cadence Incisive Enterprise Simulator running the Digital Mixed Signal option
	Cadence Mixed-Signal Solution allows users to seamlessly connect Real Value Models to the digital content
Read Full story»

Sound Design

Design Challenge
	Develop the industry’s first monolithic, 4-core audio aid
	Shrink the die size to meet a 3.8mm limit for the human ear
	Meet ultra-low power targets with customized clock timing and advanced chip stacking
Cadence Solution
	Provide a complete, production-proven, advanced digital design, implementation, and verification flow
	Mitigate risk and optimize time to productivity with expert design consulting services
Read Full story»

STMicroelectronics

Design Challenge
	Verify a 100-million-transistor IC on a tight schedule using existing verification environment
Cadence Solution
	HW-based verification system
Read full story »

STMicroelectronics Laurent Mailet-Contoz STMicroelectronics Laurent Mailet-Contoz, Project Leader from STMicroelectronics uses the Incisive verification platform at the transaction level to reduce their design cycle and help the company to be the first to new markets.

Sun Microsystems

Design Challenge
	Develop the highest throughput and most eco-responsible processor available
	Employ a verification platform that could eliminate costly respins and accelerate project completion
Cadence Solution
	Seamlessly integrated simulation, acceleration, and in-circuit emulation into a single verification environment
Read full story »

Sun Microsystems

Jai Kumar

Sun Microsystems
Jai Kumar, Verification Technologist from Sun Microsystems shared his verification experience of advanced development of UltraSPARC processors with Cadence Incisive Xtreme series.