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RF Design
Circuit design
Selectively automating non-critical aspects of RF design allows engineers to focus on precision-crafting their designs. Cadence
®
circuit design solutions enable fast and accurate entry of design concepts, which includes managing design intent in a way that flows naturally in the schematic. Using this advanced, parasitic-aware environment, designers can visualize and understand the many interdependencies of an analog, RF, or mixed-signal design, and can create and verify selected passive components.
Virtuoso Schematic Editor
Fast and flexible design entry, including well-defined component libraries.
Learn more
»
Cadence RF Design Methodology Kit
Delivers verified methodologies packaged in a system-to-tapeout RFIC design flow, demonstrated on a segment representative design.
Learn more
»
RF block simulation
Creating today’s leading-edge designs requires fast and reliable simulation and analysis of RF and high-speed integrated circuits. Cadence
®
RF block simulation technology includes the only RF simulator on the market that addresses the entire spectrum of RF design. It offers a frequency-domain harmonic balance engine for faster and accurate simulation of high dynamic-range RF circuits, and it uses a patented time-domain shooting algorithm optimized for highly non-linear circuits.
Virtuoso Analog Design Environment
The industry standard for fast and accurate design verification for custom ICs.
Learn more
»
Virtuoso Spectre Circuit Simulator
Fast, accurate SPICE-level simulation for even the most technically challenging analog and mixed-signal circuits.
Learn more
»
Virtuoso Multi-Mode Simulation
Delivers comprehensive design and verification by linking the industry’s leading simulation engines for seamless simulation throughout the design cycle.
Learn more
»
Cadence RF Design Methodology Kit
Delivers verified methodologies packaged in a system-to-tapeout RFIC design flow, demonstrated on a segment representative design.
Learn more
»
Electromagnetic analysis
Parasitics have a first-order impact on RFIC performance. Compounding this are dense layouts that result in high-frequency effects such as coupling, skin effects, substrate effects, and resonances. Cadence
®
electromagnetic modeling and analysis solutions help RF designers accurately characterize these effects for the IC fabrication process, all within an integrated design environment that shortens the path to simulation and accelerates design turnaround.
Cadence RF Design Methodology Kit
Delivers verified methodologies packaged in a system-to-tapeout RFIC design flow, demonstrated on a segment representative design.
Learn more
»
System-level simulation
Engineers need a complete flow—from system-level design to post-layout verification—that integrates circuit simulation with RF system-level and mixed-signal baseband designs. Cadence
®
technology offers flexible system-level simulation for RF and digital blocks, enabling the verification of RF blocks within a digital environment. Co-simulation capability with data-flow simulators allows system designers to explore the effects of non-ideal circuits on system architecture.
Virtuoso Analog Design Environment
The industry standard for fast and accurate design verification for custom ICs.
Learn more
»
Virtuoso AMS Designer
Flexible mixed-signal verification that links advanced Virtuoso and Incisive technologies.
Learn more
»
Virtuoso Multi-Mode Simulation
Delivers comprehensive design and verification by linking the industry’s leading simulation engines for seamless simulation throughout the design cycle.
Learn more
»
Cadence RF Design Methodology Kit
Delivers verified methodologies packaged in a system-to-tapeout RFIC design flow, demonstrated on a segment representative design.
Learn more
»
Layout
To realize RF designs, engineers need comprehensive support for custom mixed-signal and analog design at device, cell, and block levels. Cadence
®
layout solutions automate and accelerate custom block authoring. They provide advanced features for device generation and editing, block floorplanning, automatic placement, and interactive routing.
Virtuoso Layout Suite
Rapid physical layout, including automation to accelerate block authoring and simplify enforcement of advanced node process and design rules.
Learn more
»
Cadence RF Design Methodology Kit
Delivers verified methodologies packaged in a system-to-tapeout RFIC design flow, demonstrated on a segment representative design.
Learn more
»
Parasitic extraction
After layout, RF designers must go back into the design to locate parasitics and perform another round of simulation to determine where parasitic effects will cause problems. Cadence
®
solutions for parasitic extraction make it easy to get a holistic view of all the parasitic effects in a design, and then quickly correct them by flagging violations of design rules in real time.
Cadence QRC Extraction
Extracts and analyzes full-chip parasitics quickly and accurately. Accelerates timing closure and delivers higher quality of silicon.
Learn more
»
Cadence RF Design Methodology Kit
Delivers verified methodologies packaged in a system-to-tapeout RFIC design flow, demonstrated on a segment representative design.
Learn more
»
Manufacturability signoff
At today’s advanced technology nodes, RF design software must account for the challenges of smaller transistors and wires, as well as the data capacity and complexity challenges of denser, more intricate chips. Cadence
®
solutions for manufacturability take the knowledge of creating the mask and how the chip is going to be manufactured and bring it back into the design phase. This helps designers compensate for physical effects while providing a reliable way to achieve manufacturing signoff before tapeout.
Virtuoso Layout Migrate
Rapid physical layout migration, including support for complex design rules at advanced nodes.
Learn more
»
Virtuoso Layout Suite
Rapid physical layout, including automation to accelerate block authoring and simplify enforcement of advanced node process and design rules.
Learn more
»
Virtuoso Analog Design Environment
The industry standard for fast and accurate design verification for custom ICs.
Learn more
»
Assura Physical Verification
Performs design rule checking and layout vs. schematic verification to deliver high-yielding custom IP.
Learn more
»
Assura Physical Verification
Performs design rule checking and layout vs. schematic verification to deliver high-yielding custom IP.
Learn more
»
Cadence QRC Extraction
Extracts and analyzes full-chip parasitics quickly and accurately. Accelerates timing closure and delivers higher quality of silicon.
Learn more
»
Cadence RF Design Methodology Kit
Delivers verified methodologies packaged in a system-to-tapeout RFIC design flow, demonstrated on a segment representative design.
Learn more
»
Virtuoso AMS Designer
Flexible mixed-signal verification that links advanced Virtuoso and Incisive technologies.
Learn more
»
Virtuoso Analog Design Environment
The industry standard for fast and accurate design verification for custom ICs.
Learn more
»
Virtuoso Layout Migrate
Rapid physical layout migration, including support for complex design rules at advanced nodes.
Learn more
»
Virtuoso Layout Suite
Rapid physical layout, including automation to accelerate block authoring and simplify enforcement of advanced node process and design rules.
Learn more
»
Virtuoso Multi-Mode Simulation
Delivers comprehensive design and verification by linking the industry’s leading simulation engines for seamless simulation throughout the design cycle.
Learn more
»
Virtuoso Schematic Editor
Fast and flexible design entry, including well-defined component libraries.
Learn more
»
Virtuoso Spectre Circuit Simulator
Fast, accurate SPICE-level simulation for even the most technically challenging analog and mixed-signal circuits.
Learn more
»
Content Query Web Part [1]
Key RF Technologies from Cadence Qualified for TSMC 65-Nanometer Node
RFIC Design Using Virtuoso RF Designer Technical Brief
speakTECH Feeder Viewer for Community Server
Recent Blog Posts
RF Measurement Library: Capturing Circuit Characterization Setups on the Schematic
Periodic Steady-State Analysis for DC-to-DC Converters
Join us at the Cadence booth at the International Microwave Symposium
Visit the Community
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Content Query Web Part [2]
Cadence Services
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